7400S Search Results

barcode reader using avr

Abstract: KEYPAD 4 X 4 verilog KEYPAD verilog rfid reader v6.0 cpld kit verilog keypad scanner cpld keypad encoder schematic ATDS1500PC programmable slew rate control IO
Contextual Info: Programmable Logic and Systems EPLD Family Overview Density 5 V – ATF15xxAS CPLD 3.3 V – ATF15xxASV SPLD ATF22V10C, LVC ATF16V8B/C, LVC ATF750C/LVC Decoders, Glue Logic, can be used to replace a few 7400series TTL 1.8 V – ATF15xxBE State machines, Timing, Control,

transistor cms 6BW

Abstract: g2v2 relay 4 digit 7 segment calculator lcd display pin BIT 31936 g2v2 transistor 5bw A7102A 6BW 87 automatic dialer sd 7402
Contextual Info: DEFINITY Enterprise Communications Server and System 75 and System 85 Terminals and Adjuncts Reference 555-015-201 Comcode 108603994 Issue 11 December 1999 Copyright  1999, Lucent Technologies All Rights Reserved Printed in USA Notice Every effort was made to ensure that the information in this book was

31-oq

Abstract: 7C342-25 CY7C342-35HMB 7C342-35 CY7C342 CY7C342B OQ11
Contextual Info: CY7C342 CY7C342B rif CYPRESS 128-Macrocell M AX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342

7400series

Abstract: cmos logic 7400 series 7400 family TTL 7400-series EPM5016
Contextual Info: The Complete Industry-Standard Programm able Logic Family MAX 5000 EPLDs 384 EPM5192 tpp = 25 ns - C/> 0> .c o 3 08 EPM5128 tpp —25 ns 256 CO Q. A EPM5130 tpp —25 ns O / ca> D EPM5064, tPD = 25 ns 128 ▲ EPM5032, tPD = 15 ns 64 ▲ EPM5016, tPD = 15 ns

D5032

Abstract: IC TTL 7400 free J1810 Altera LP5 PLDS-ENCORE plej5128
Contextual Info: PLDS-ENCORE MAX+PLUS, A+PLUS & SAM+PLUS Programmable Logic Development System Data Sheet September 1991, ver. 2 Contents □ □ □ □ □ General Description P L S -M A X — M A X + P L U S P ro g ra m m ab le Logic Softw are P L S - S U P R E M E — A + P L U S P ro g ra m m a b le L ogic Softw are

J-Lead, QFP ceramic

Abstract: IC 7400 SERIES book EPM 5192
Contextual Info: M A X 5000 Programmable Logic Device Family March 1995, ver. 2 Features. D a ta she et • ■ ■ ■ ■ ■ ■ Advanced M ultiple Array M atrix MAX 5000 architecture com bining speed and ease-of-use of PAL devices w ith density of program m able gate arrays

K12J

Abstract: 100-PIN CY7C346 CY7C346B f 7400
Contextual Info: CY7C346 CY7C346B 5T CYPRESS 128-Macrocell MAX EPLDs Features Functional Description • 128 macrocells in 8 LABs • 20 dedicated inputs, up to 64 bidirec­ tional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C346

74x175

Contextual Info: M/C2563A MIC2563A Dual Slot PCMCIA/CardBus Power Controller •v? Preliminary Information General Description Applications The MIC2563A Dual Slot PCMCIA Personal Computer Memory Card International Association and CardBus Power Controller handles all PC Card slot power supply pins, both

LS7400

Abstract: internal structure 74LS00 nand gate 7404 ic draw pin configuration of ic 7404 D flip-flop 74175 pin data sheet 7404 inverter spice amd386 cdi schematics pcb 7400 spice model 74ls00
Contextual Info: Schematic Entry User Manual August 1994 090-0602-001 Data I/O has made every attempt to ensure that the information in this document is accurate and complete. Data I/O assumes no liability for errors, or for any incidental, consequential, indirect or special damages, including, without limitation, loss of use,

7486 XOR gate

Abstract: 8mcomp XOR 7486 Truth Table 74192 4count XOR 7486 GATE 16cudslr 7472 truth table 7486 xor 74194 truth table
Contextual Info: PROGRAMMABL E a \ l o g ic s o f t w a r e I-WV i1 I— rT -U U PLS-MAX =Er - ]T — n V n i n ni l A V P L S -m A X MAX+PLUS FEATURES GENERAL DESCRIPTION • Unified Development system for the entire Multiple Array Matrix MAX family of EPLDs. • Multiple design entry methods including a hier­

c341 transistor

Abstract: 7C341 diode c341 CY7C341 84-PIN C341
Contextual Info: 41 CY7C341 192-Macrocell MAX EPLD Features • • • • • • 192 macrocells in 12 LABs 8 dedicated inputs, 64 bidirectional I/O pin 0.8-micron double-metal CMOS EPROM technology Programmable interconnect array 384 expander product terms Available in 84-pin HLCC, PLCC, and PGA packages

TL494 car charger schematic diagram

Abstract: samsung galaxy s2 controller for PWM fan tl494 1A current to 0-5v voltage converter using LM317 SMD LD33 capacitor huang 2200uF 35V uc3843 flyback supply opto-coupler SMD MOSFET DRIVE 4606 schematic lcd inverter samsung sine wave inverter tl494 circuit diagram
Contextual Info: Micrel Semiconductor 1997 Databook 1 _ General Information 2 _ Computer Peripherals 3 _ Low-Dropout Linear Voltage Regulators 4 _ Switch-Mode Voltage Regulators 5 _ MOSFET Drivers 6 _

asynchronous fifo vhdl

Abstract: 8 BIT ALU design with verilog/vhdl code full subtractor using ic 74138 74139 for bcd to excess 3 code vhdl code for 8bit bcd to seven segment display 32 BIT ALU design with verilog/vhdl code 74594 16 BIT ALU design with verilog/vhdl code B1516 RAM1024
Contextual Info: QuickWorks User Manual with SpDE Reference Release 2009.2.1 Contact Information QuickLogic Corporation 1277 Orleans Drive Sunnyvale, CA 94089 Phone: (408) 990-4000 (US) (905) 940-4149 (Canada) +(44) 1932-57-9011 (Europe) +(852) 2567-5441 (Asia) E-mail: info@quicklogic.com

c3415

Abstract: cy7c341-30jc CY7C341
Contextual Info: CY7C341 y CYPRESS Features • • • • • • 192 macrocells in 12 LABs 8 dedicated inputs, 64 bidirectional I/O pin 0.8-micron double-metal CMOS EPROM technology Programmable interconnect array 384 expander product terms Available in 84-pin HLCC, PLCC, and PGA packages

Contextual Info: EPM5192 EPLD p 0 3 tlirG S -I □ □ □ □ General _ . 192 macrocells for easy replacement of over 100 TTL devices and for integration of complete logic boards into a single package 384 shareable expander product terms that offer flexibility for register

programming manual EPLD EPS448

Abstract: Altera EPM5128 EPM7064-12 leap u1 EP-900910 PLE3-12a tcl tv circuit altera eplds EP610 "pin compatible" ALTERA MAX 5000
Contextual Info: Data Book TENTH ANNIVERSARY A Decade of Leadership A u g u s t 1993 Data Book August 1993 A-DB-0793-01 Altera, MAX, and M A X+PLUS are registered trademarks of Altera Corporation. The following, among others, are trademarks of Altera Corporation: AHDL, M AX+PLUS II, PL-ASAP2, PLDS-HPS, PLS-ADV, PLS-ES, PLS-FLEX8, PLS-FLEX8/H P, PLS-FLEX8/SN , PLS-HPS, PLS-STD, PLS-W S/H P,

342-35HM

Contextual Info: CY7C342 CYPRESS SEMICONDUCTOR Features 128-Macrocell MAX EPLDs M A X architecture is 100% u ser configur­ able, allowing the devices to accom m o­ d a te a variety o f in d ependent logic func­ tions. • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional

100-PIN

Abstract: CY7C346 ULTRA37000TM
Contextual Info: USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 128-Macrocell MAX EPLD Features The 128 macrocells in the CY7C346 are divided into eight LABs, 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each

ix 2933

Abstract: transistor quang 7400 TTL ix 2933 data sheet schematic XOR Gates 7400 chip 7400 series pin connection CF160 schematic diagram inverter PF100
Contextual Info: QuickWorks User's Guide with SpDE™ Reference June 1996 Copyright Information Copyright 1991-1996 QuickLogic Corporation. All rights reserved. The information contained in this manual and the accompanying software program are protected by copyright; all rights are reserved by QuickLogic Corporation.

FUNCTIONAL DIAGRAM OF 7400

Abstract: pin diagram 7400 series 7400 PIN DIAGRAM schematic diagram TMS34010 7400 series logic ICs 7400 TTL 7400 chip 7400 fan-out 7400 functional diagram TTL 7400
Contextual Info: QAN8 Video Support Logic and VME Interface Dan Le Vasseur INTRODUCTION This application note describes how a video board based on the TMS34020 Graphics Processor was designed using a QuickLogic pASIC device to implement a complete VME slave interface and all the high-speed video

C3424

Abstract: 68-PIN 7C342-30 7C342-35 CY7C342 CY7C342B C3422 CY7C342-30HC CY7C342B-30RMB 30RM
Contextual Info: CY7C342 CY7C342B CYPRESS 128-Macrocell MAX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342

Altera EPM5128

Abstract: WKX 62 EPM5016 epm5130 pinouts for 7400 series EPM5064 EPM5192 program EPM5032 EPM5128 PACKAGING PLDS-MAX
Contextual Info: EPM5016 to EPM5192 EPLDs High-Speed, High-Density MAX 5000 Devices Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ Complete family of CMOS EPLDs solves design tasks ranging from fast 20-pin address decoders to 100-pin LSI custom peripherals.

transistor a2160

Abstract: transistor A1270 A1270 transistor transistor 2sD 4515 1431T transistor transistor A769 mn15151 mini circuits 15542 A1270 Y AN 5606K
Contextual Info: Type Number List • Integrated Circuits MOS LSIs M O S L S Is Page Type No, M N 5117 M N171605 32,42 AM N18P83221 43 M N 3671A 62 M N 5126 87 43 M N 3672 62 M N 5128 87 37 ,4 4,45 46 M N 1256 46 M N 1258 46 M N 1259 46 M N12861 46 M N 12862 46 M N 187124

68-PIN

Abstract: CY7C342B ULTRA37000TM CY7C342B-30JC
Contextual Info: USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C342B 128-Macrocell MAX EPLD Features 100% user-configurable, allowing the device to accommodate a variety of independent logic functions. • 128 macrocells in eight logic array blocks LABs The 128 macrocells in the CY7C342B are divided into eight