74AC273 Search Results

EEL 19s

Contextual Info: 74AC273 Octal D-Type Flip-Flop General Description is required and th e C lock and M aster R eset are com m on to all storage elem ents. The AC 273 has e ight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. T h e com m on buff­

0c002

Contextual Info: Semi co n d u August 1993 t o r 54AC/74AC273 Octal D Flip-Flop General Description Features The ’273 has eight edge-triggered D-type flip-flops with indi­ vidual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input load and reset (clear) all

Contextual Info: 74AC273, 74ACT273 Octal D-Type Flip-Flop Features General Description • Ideal buffer for microprocessor or memory The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock CP and Master

Contextual Info: November Revised D ecem ber 1998 S E M IC O N D U C T O R TM 74AC273 Octal D-Type Flip-Flop General Description is required and the C lock and M aster R eset are com m on to all storage elem ents. The AC 273 has e ig h t edge-triggered D-type flip-flops with

74AC273

Abstract: 74AC273MTC 74AC273PC 74AC273SC 74AC273SJ AC273 M20D MS-013 MTC20 74AC273P
Contextual Info: A IR C H N ovem ber 1988 . I l— O Revised D ecem ber 1998 S E M IC Ü N D U C T Ü R tm 74AC273 Octal D-Type Flip-Flop General Description is required and the C lock and M aster Reset are com m on to all storage elem ents. T he AC 273 has eight edge-triggered D -type flip-flops with

74AC

Abstract: AC273
Contextual Info: August 1993 Semiconductor 54AC/74AC273 Octal D Flip-Flop General Description Features The ’273 has eight edge-triggered D-type flip-flops with indi­ vidual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input load and reset (clear) all

74AC273

Abstract: 74AC273MTC 74AC273PC 74AC273SC 74AC273SJ 74ACT273 74ACT273SC 74ACT273SJ AC273 ACT273
Contextual Info: Revised March 2005 74AC273 • 74ACT273 Octal D-Type Flip-Flop General Description Features The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input

ACT273

Contextual Info: AC273 • ACT273 54AC/74AC273 • 54ACT/74ACT273 Octal D Flip-Flop Description Connection Diagrams The ’AC/’ACT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip-flops

74AC273

Contextual Info: S G S -T H O M S O N [MSIfiiSilLiSìlKìtÉfflOSS 74AC273 OCTAL D-TYPE FLIP FLOP WITH CLEAR PRELIM IN ARY DATA . HIGHSPEED: fMAX = 190 MHz TYP. at Vcc =5V . LOW POWER DISSIPATION: Icc = 8 |xA (MAX.) at Ta = 25 °C . HIGH NOISE IMMUNITY: V nih = V nil = 28% V cc (MIN.)

AC273

Abstract: 74AC273 74AC273B 74AC273M DIP-20
Contextual Info: 74AC273  OCTAL D-TYPE FLIP FLOP WITH CLEAR PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 190 MHz TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING

Contextual Info: H A R R I SS E M I C O N DS E C T O R 37E D H M3D2271 0 325522 t >*HAS Technical u a t a _ J_ _ CD54/74AC273 CD54/74A C T273 - " F ^ U -D X l Octal D Flip-Flop with Reset Type Features:

cd74ac273

Abstract: 74ACT273
Contextual Info: Technical Data _ CD54/74AC273 CD54/74ACT273 Octal D Flip-Flop with Reset Type Feature»: • B uffered inputs a Typical propagation delay: 6.5 ns @ Vcc - 5 V, 7V = 25° C, CL = 50 pF The RCA CD54/74AC273 and CD54/74ACT273 are octal D flip -flo p s w ith reset that use the RCA ADVANCED CMOS

Contextual Info: 74AC273 Octal D-Type Flip-Flop General Description The AC273 has eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buff­ ered Clock CP and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously.

smd code dn

Abstract: 74AC 74AC273 AC273 C1995 E20A J20A N20B
Contextual Info: 54AC 74AC273 Octal D Flip-Flop General Description Features The ’273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock CP and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously

AC273

Abstract: 74AC273 74AC273MTC 74AC273PC 74AC273SC 74AC273SJ M20D MTC20
Contextual Info: Revised December 1998 74AC273 Octal D-Type Flip-Flop General Description The AC273 has eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously.

74AC273

Abstract: 74AC273MTC 74AC273PC 74AC273SC 74AC273SJ 74ACT273 74ACT273SC 74ACT273SJ AC273 ACT273
Contextual Info: 74AC273, 74ACT273 Octal D-Type Flip-Flop Features General Description • Ideal buffer for microprocessor or memory The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock CP and Master

74ACT273SC

Abstract: AC273 74AC273 74AC273MTC 74AC273PC 74AC273SC 74AC273SJ 74ACT273 74ACT273MTC ACT273
Contextual Info: Revised October 1999 74AC273 • 74ACT273 Octal D-Type Flip-Flop General Description Features The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input

74AC273

Abstract: 74AC273B 74AC273M 74AC273MTR 74AC273TTR DIP-20
Contextual Info: 74AC273 OCTAL D-TYPE FLIP FLOP WITH CLEAR • ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 250MHz TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 8µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING

ic data AC273

Abstract: sc1046 74AC273 74AC273B 74AC273M AC273 DIP-20
Contextual Info: SGS-THOMSON 74AC273 M IM i[Li gïïlHΩiD(3S OCTAL D-TYPE FLIP FLOP W ITH CLEAR P R E L IM IN A R Y D A T A . . . . . . HIGHSPEED: fMAX = 190 MHz (TYP.) at Vcc =5V LOW POWER DISSIPATION: Icc = 8 |xA (MAX.) at T a = 25 °C HIGH NOISE IMMUNITY: V n ih = V n il = 2 8 % V c c (MIN.)

ACT273

Abstract: ac273 74AC
Contextual Info: AC273 • ACT273 54AC/74AC273 • 54ACT/74ACT273 O ctal D Flip-Flop Description Connection Diagrams The ’AC/’ACT273 has e ig h t edge-triggered D-type flip -flo p s w ith individual D in p u ts and Q outputs. The com m on buffered C lock CP and M aster Reset

Contextual Info: Technical Data _ CD54/74AC273 CD54/74ACT273 Octal D Flip-Flop with Reset Type Features: • Buffered inputs m Typical propagation delay: 6.5 n s @ V cc = 5 V, I * = 25° C, CL ; 50 pF RESET THU 1 M C S-S6»76R 2 FUNCTIONAL DIAGRAM The RCA CD54/74AC273 and CD54/74ACT273 are octal D

74AC273

Contextual Info: 74AC273 OCTAL D-TYPE FLIP FLOP WITH CLEAR P R ELIM IN ARY DATA . HIGHSPEED: fM A X = 190 MHz TYP. at Vcc =5V . LOW POWER DISSIPATION: Ice = 8 jiA (MAX.) at T a = 25 °C . HIGH NOISE IMMUNITY: V nih = V nil = 2 8 % Vcc (MIN.) • 50£2 TRANSMISSION LINE DRIVING

ACT273

Abstract: AC273
Contextual Info: AC273 • ACT273 54AC/74AC273 • 54ACT/74ACT273 Octal D Flip-Flop Description Connection Diagrams The ’AC/’ACT273 has eight edge-triggered D-type flip-flops w ith individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (15ÎÏÏ) inputs load and reset (clear) all flip-flops

ACT273

Abstract: 74AC mr 800 diode CP000
Contextual Info: National Semiconductor 54AC/74AC273 • 54ACT/74ACT273 Octal D Flip-Flop General Description Features The ’A C /’ACT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buff­ ered Clock CP and Master Reset (MR) input load and re­