74AC280 Search Results

AC280

Abstract: CD54AC280F3A CD54ACT280F3A CD74AC280E CD74AC280M CD74ACT280E
Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

Contextual Info: Technical Data _ CD54/74AC280 CD54/74ACT280 9-Bit Odd/Even Parity Generator/Checker V cc"4 Type Features: • B uffered inputs u Typical propagation delay: 10 ns @ V Cc = 5 V, T, = 25°C, CL = 50 pF GND- 7 FUNCTIONAL DIAGRAM The RCA CD54/74AC280 and CD54/74ACT280 9 -b it o d d /

74AC

Abstract: 74AC280 74AC280SC AC280 M14A
Contextual Info: Revised December 1998 74AC280 9-Bit Parity Generator/Checker General Description Features The AC280 is a high-speed parity generator/checker that accepts nine bits of input data and detects whether an even or an odd number of these inputs is HIGH. If an even

cd74ac280

Abstract: 74ac280
Contextual Info: Technical Data _ CD54/74AC280 CD54/74ACT280 9-Bit Odd/Even Parity Generator/Checker £ EVEN X ODD Type Features: NC« 3 3 ZCS- 3 M VCC "14 • B uttered inputs ■ Typical propagation delay: 10 ns @ Vtx - 5 V, T„ = 25°C, C l = 50 pF 6 NO* ? FUNCTIONAL DIAGRAM

74ac280

Contextual Info: T e c h n ic a l D a la - . . CD54/74AC280 CD54/74ACT280 9-Bit Odd/Even Parity Generator/Checker X CVCN t 01» NC.3 Vç ç 9 2 CS-5M H » 4 ONO» T Type Features: • Buffered inputs m Typical propagation delay: 10 ns @ Vcc = 5 V, U = 25° C, C l = 50 pF FUNCTIONAL DIAGRAM

AC280

Abstract: CD54AC280F3A CD54ACT280F3A CD74AC280E CD74AC280M CD74ACT280E
Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

74AC280

Abstract: 74AC280B 74AC280M 74AC280MTR 74AC280TTR TSSOP14
Contextual Info: 74AC280 9 BIT PARITY GENERATOR • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 6ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:

Contextual Info: I R C H November 1988 iL D s e m ic o n d u c t o r Revised November 1999 74AC280 9-Bit Parity Generator/Checker General Description Features The AC280 is a high-speed parity generator/checker that accepts nine bits of input data and detects whether an

AC280

Abstract: CD54AC280F3A CD54ACT280F3A CD74AC280E CD74AC280M CD74ACT280E
Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

Contextual Info: Technical Data _ CD54/74AC280 CD54/74ACT280 9-Bit Odd/Even Parity Generator/Checker I EVEN Z ODD NC* 3 VCC -14 GNO* 7 »¿fcs-'WH Type Features: • Buffered inputs m Typical propagation delay: 1 0 n s @ Vcc = 5 V, rA= 25° C, CL= 50 pF FUNCTIONAL DIAGRAM

AC280

Abstract: CD54AC280F3A CD54ACT280F3A CD74AC280E CD74AC280M CD74ACT280E
Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

74AC280

Abstract: 74AC280B 74AC280M AC280
Contextual Info:  74AC280 9 BIT PARITY GENERATOR • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4 ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY

Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

EDR-7320

Abstract: 74AC280 74AC280SC 74AC280SJ AC280 M14A M14D
Contextual Info: A I R C H I L D Revised N ovem ber 1999 S E M I C O N D U C T O R TM 74AC280 9-Bit Parity Generator/Checker General Description Features The A C 280 is a high-speed parity g enerator/checker that accepts nine bits of input d ata and detects w he th e r an

74AC

Abstract: 99555
Contextual Info: o 00 CM C Tl National JSjA Semiconductor 54AC/74AC280 • 54ACT/74ACT280 9-Bit Parity Generator/Checker Features General Description The 'A C /’ACT280 is a high-speed parity generator/checker that accepts nine bits of input data and detects whether an even or an odd number of these inputs is HIGH. If an even

74AC

Abstract: 74AC280 74AC280SC AC280 M14A L35-10 Diode MFW 24
Contextual Info: Revised D ecem ber 1998 S E M I C O N D U C T O R TM 74AC280 9-Bit Parity Generator/Checker General Description Features T h e AC 280 is a high-speed parity generator/checker that accepts nine bits of input data and detects w he th e r an even o r an odd num ber of these inputs is HIGH. If an even

Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

AC280

Abstract: CD54AC280F3A CD54ACT280F3A CD74AC280E CD74AC280M CD74ACT280E
Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

Contextual Info: S 3 N a t i o n a l ÆM Semiconductor 54AC/74AC280 9-Bit Parity Generator/Checker General Description Features The ’AC280 is a high-speed parity generator/checker that accepts nine bits of input data and detects whether an even or an odd number of these inputs is HIGH. If an even num­

AC280

Abstract: CD54AC280F3A CD54ACT280F3A CD74AC280E CD74AC280M CD74ACT280E
Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

74AC280

Abstract: 74AC280B 74AC280M 74AC280MTR 74AC280TTR TSSOP14
Contextual Info: 74AC280 9 BIT PARITY GENERATOR • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 6ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:

Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity