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Rochester Electronics LLC 74ACT11020DR IC GATE NAND 4-INP
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	74ACT11020DR	Bulk	2,157		662	1 - 10 - 100 - 1000 $0.45 10000 $0.45	Buy Now
Texas Instruments 74ACT11020DR 74ACT11020DR
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Verical	74ACT11020DR		2,157		765	1 - 10 - 100 - 1000 $0.4524 10000 $0.4033	Buy Now
Rochester Electronics	74ACT11020DR		2,157		1	1 - 10 - 100 $0.436 1000 $0.3619 10000 $0.3226	Buy Now
Texas Instruments 74ACT11020N INSTOCK
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Chip 1 Exchange	74ACT11020N		300			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Vyrian	74ACT11020N		1,194			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Texas Instruments SN74ACT11020N Peripheral ICs
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Vyrian	SN74ACT11020N		877			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Texas Instruments 74ACT11020D Peripheral ICs
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Vyrian	74ACT11020D		498			1 - 10 - 100 - 1000 - 10000 -	Get Quote

74ACT11020 Datasheets (7)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF	PDF Size	Page count
74ACT11020		Texas Instruments	DUAL 4-INPUT POSITIVE-NAND GATES		Original	PDF	71.62KB	4
74ACT11020		Texas Instruments	DUAL 4-INPUT POSITIVE-NAND GATES		Original	PDF	65.62KB	5
74ACT11020D		Texas Instruments	DUAL 4-INPUT POSITIVE-NAND GATE		Original	PDF	65.63KB	5
74ACT11020D		Unknown	Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.		Historical	PDF	36.75KB	1
74ACT11020DR		Texas Instruments	Dual 4-Input Positive-nand Gates		Original	PDF	65.64KB	5
74ACT11020N		Texas Instruments	DUAL 4-INPUT POSITIVE-NAND GATE		Original	PDF	65.63KB	5
74ACT11020N		Unknown	Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.		Historical	PDF	36.75KB	1

74ACT11020 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES TI0053— D 2957, JUNE 1987— REVISED JANUARY 1990 • Inputs are TTL-Voltage Compatible 54ACT11020 . . . J PACKAGE 74ACT11020 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout	OCR Scan	54ACT11020, 74ACT11020 TI0053-- 54ACT11020 74ACT11020 500-mA 300-mil	PDF
Contextual Info: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES SCAS016A - D2957, JUNE 1987 - REVISED APRIL 1993 • * Inputs Are TTL-Voltage Compatible ■ ■ * Flow-Through Architecture to Optimize PCB Layout I I * Center-Pin V^c and GND Configurations to Minimize High-Speed Switching Noise	OCR Scan	54ACT11020, 74ACT11020 SCAS016A D2957, 54ACT11020. 500-mA 300-mil	PDF
54ACT11020 Abstract: 74ACT11020 D2957 Contextual Info: 54ACT11020, 74ACT11020 DUAL 4ĆINPUT POSITIVEĆNAND GATES ą ą SCAS016A − D2957, JUNE 1987 − REVISED APRIL 1993 • • • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations to	Original	54ACT11020, 74ACT11020 SCAS016A D2957, 500-mA 300-mil 54ACT11020 54ACT11020 74ACT11020 D2957	PDF
54ACT11020 Abstract: 74ACT11020 D2957 9n10 Contextual Info: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES TI0053— D2957, JU N E 1987— REVISED JA N U A R Y 1990 • Inputs are TTL-Voltage Compatible 5 4 A C T 1 1020 . . . J P ACKA G E 7 4 A C T 11 0 20 . . . D OR N P ACKA G E Flow-Through Architecture to Optimize PCB	OCR Scan	54ACT11020, 74ACT11020 TI0053â D2957, 500-mA 300-mil 54ACT11020 74ACT11020 D2957 9n10	PDF
CT1102 Abstract: 54ACT11020 74ACT11020 D2957 692B Contextual Info: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES SCAS016A - D2957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout 54A C T11020. . . J PACKAGE 74ACT11020 . . . D OR N PACKAGE TOP VIEW	OCR Scan	54ACT11020, 74ACT11020 SCAS016A D2957, 500-mA 300-mll 54ACT11020. 74ACT11020 T4EC11 CT1102 54ACT11020 D2957 692B	PDF
Contextual Info: 54ACT11020,74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES SCAS016A - 02957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible 54ACT11020. . . J PACKAGE 74ACT11020. . . D OR N PACKAGE TOP VIEW Flow-Through Architecture to Optimize PCB Layout Center-Pin Vqc and GND Configurations to	OCR Scan	54ACT11020 74ACT11020 SCAS016A 500-mA 300-mil 54ACT11020. 74ACT11020. 54ACT11020	PDF
Contextual Info: 54ACT11020, 74ACT11020 DUAL 4ĆINPUT POSITIVEĆNAND GATES ą ą SCAS016A − D2957, JUNE 1987 − REVISED APRIL 1993 • • • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations to	Original	54ACT11020, 74ACT11020 SCAS016A D2957, 500-mA 300-mil 54ACT11020	PDF
54ACT11020 Abstract: 74ACT11020 D2957 Contextual Info: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES SCAS016A – D2957, JUNE 1987 – REVISED APRIL 1993 • • • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations to	Original	54ACT11020, 74ACT11020 SCAS016A D2957, 500-mA 300-mil 54ACT11020 54ACT1102customer 54ACT11020 74ACT11020 D2957	PDF
54ACT11020 Abstract: 74ACT11020 D2957 Contextual Info: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES SCAS016A – D2957, JUNE 1987 – REVISED APRIL 1993 • • • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations to	Original	54ACT11020, 74ACT11020 SCAS016A D2957, 500-mA 300-mil 54ACT11020 54ACT1102ocal 54ACT11020 74ACT11020 D2957	PDF