74AUP1G32 Search Results

Contextual Info: 74AUP1G32-Q100 Low-power 2-input OR-gate Rev. 2 — 4 July 2013 Product data sheet 1. General description The 74AUP1G32-Q100 provides the single 2-input OR function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

74AUP1G32

Abstract: 74AUP1G32GF 74AUP1G32GM 74AUP1G32GW JESD22-A114-C MO-203
Contextual Info: 74AUP1G32 Low-power 2-input OR gate Rev. 02 — 21 July 2006 Product data sheet 1. General description The 74AUP1G32 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

74AUP1G3208

Abstract: 74AUP1G3208GF 74AUP1G3208GM 74AUP1G3208GW
Contextual Info: 74AUP1G3208 Low-power 3-input OR-AND gate Rev. 3 — 11 October 2010 Product data sheet 1. General description The 74AUP1G3208 provides the Boolean function: Y = A + B x C. The user can choose the logic functions OR, AND and OR-AND. All inputs can be connected to VCC or GND.

Contextual Info: 74AUP1G32 SINGLE 2 INPUT POSITIVE OR GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G32 is a single 2-input positive OR gate with a standard

Contextual Info: 74AUP1G32 Low-power 2-input OR-gate Rev. 4 — 23 November 2011 Product data sheet 1. General description The 74AUP1G32 provides the single 2-input OR function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

74AUP1G32

Abstract: A115-A C101 SOT-665 74AUP1G32D sot665 equivalent
Contextual Info: 74AUP1G32 Low power single 2-input OR gate Features • High speed: tPD = 5.8 ns max. at VCC = 2.3 V ■ Power down protection on inputs and outputs ■ Balanced propagation delays: tPLH ≈ tPHL ■ Operating voltage range: VCC (opr) = 1.2 to 3.6 V ■

Contextual Info: 74AUP1G32 SINGLE 2 INPUT POSITIVE OR GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. ( Top View ) ( Top View ) The 74AUP1G32 is a single 2-input positive OR gate with a standard

Contextual Info: 74AUP1G32-Q100 Low-power 2-input OR-gate Rev. 1 — 20 March 2013 Product data sheet 1. General description The 74AUP1G32-Q100 provides the single 2-input OR function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

74AUP1G32

Abstract: 74AUP1G32GM 74AUP1G32GW JESD22-A114-C MO-203
Contextual Info: 74AUP1G32 Low-power 2-input OR gate Rev. 01 — 2 August 2005 Product data sheet 1. General description The 74AUP1G32 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

74AUP1G3208

Abstract: 74AUP1G3208GF 74AUP1G3208GM 74AUP1G3208GW
Contextual Info: 74AUP1G3208 Low-power 3-input OR-AND gate Rev. 01 — 29 November 2006 Product data sheet 1. General description The 74AUP1G3208 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

Contextual Info: 74AUP1G32 Low-power buffer with open-drain and buffer Rev. 6 — 5 July 2013 Product data sheet 1. General description The 74AUP1G32 provides the single 2-input OR function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

Contextual Info: 74AUP1G32 SINGLE 2 INPUT POSITIVE OR GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G32 is a single 2-input positive OR gate with a standard

74AUP1G3208

Abstract: 74AUP1G3208GF 74AUP1G3208GM 74AUP1G3208GW JESD22-A114-C
Contextual Info: 74AUP1G3208 Low-power 3-input OR-AND gate Rev. 01.00 — 17 January 2006 Preliminary data sheet 1. General description The 74AUP1G3208 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Contextual Info: 74AUP1G32 Low-power 2-input OR-gate Rev. 5 — 28 June 2012 Product data sheet 1. General description The 74AUP1G32 provides the single 2-input OR function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

74AUP1G3208

Abstract: 74AUP1G3208GF 74AUP1G3208GM 74AUP1G3208GW JESD22-A114E
Contextual Info: 74AUP1G3208 Low-power 3-input OR-AND gate Rev. 02 — 3 July 2009 Product data sheet 1. General description The 74AUP1G3208 provides the Boolean function: Y = A + B x C. The user can choose the logic functions OR, AND and OR-AND. All inputs can be connected to VCC or GND.

Contextual Info: 74AUP1G3208 Low-power 3-input OR-AND gate Rev. 5 — 22 June 2012 Product data sheet 1. General description The 74AUP1G3208 provides the Boolean function: Y = A + B x C. The user can choose the logic functions OR, AND and OR-AND. All inputs can be connected to VCC or GND.

Contextual Info: 74AUP1G32 Low power single 2-input OR gate Features • High speed: tPD = 5.8 ns max. at VCC = 2.3 V ■ Power down protection on inputs and outputs ■ Balanced propagation delays: tPLH ≈ tPHL ■ Operating voltage range: VCC (opr) = 1.2 to 3.6 V ■

74AUP1G32GF

Abstract: 74AUP1G32 74AUP1G32GM 74AUP1G32GW
Contextual Info: 74AUP1G32 Low-power 2-input OR-gate Rev. 3 — 12 October 2010 Product data sheet 1. General description The 74AUP1G32 provides the single 2-input OR function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

Contextual Info: 74AUP1G32 Low-power 2-input OR-gate Rev. 7 — 8 July 2013 Product data sheet 1. General description The 74AUP1G32 provides the single 2-input OR function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

Contextual Info: 74AUP1G32 Low-power 2-input OR gate Rev. 02 — 2 August 2005 Product data sheet 1. General description The 74AUP1G32 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

Contextual Info: 74AUP1G3208 Low-power 3-input OR-AND gate Rev. 5 — 22 June 2012 Product data sheet 1. General description The 74AUP1G3208 provides the Boolean function: Y = A + B x C. The user can choose the logic functions OR, AND and OR-AND. All inputs can be connected to VCC or GND.

Contextual Info: 74AUP1G3208 Low-power 3-input OR-AND gate Rev. 4 — 23 November 2011 Product data sheet 1. General description The 74AUP1G3208 provides the Boolean function: Y = A + B  C. The user can choose the logic functions OR, AND and OR-AND. All inputs can be connected to VCC or GND.

74AUP1G126

Abstract: 74AUP1G32 JESD22-A114E 74AUP1T1326
Contextual Info: 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state Rev. 01 — 20 January 2009 Product data sheet 1. General description The 74AUP1T1326 is a high-performance, low-power, low-voltage, single-bit, dual supply buffer/line driver with output enable circuitry.

schematic diagram atx Power supply 500w

Abstract: pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS
Contextual Info: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 Digital Signal Processors, iCoupler , iMEMS® and iSensor . . . . . 805, 2707, 2768-2769 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-568 RF Connectors . . . . . . . . . . . . . . . . . . . . . . Pages 454-455