74AUP1G38 Search Results

Contextual Info: 74AUP1G38 Low-power 2-input NAND gate open drain Rev. 01 — 20 October 2006 Product data sheet 1. General description The 74AUP1G38 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Contextual Info: 74AUP1G38 Low-power 2-input NAND gate open drain Rev. 6 — 28 June 2012 Product data sheet 1. General description The 74AUP1G38 provides the single 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to

74AUP1G386

Abstract: 74AUP1G386GF 74AUP1G386GM 74AUP1G386GW 74AUP1G386GN
Contextual Info: 74AUP1G386 Low-power 3-input EXCLUSIVE-OR gate Rev. 4 — 5 August 2010 Product data sheet 1. General description The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

74AUP1G38GM

Abstract: 74AUP1G38GW JESD22-A114E MO-203 74AUP1G38GF
Contextual Info: 74AUP1G38 Low-power 2-input NAND gate open drain Rev. 03 — 22 June 2009 Product data sheet 1. General description The 74AUP1G38 provides the single 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to

Contextual Info: 74AUP1G38 Low-power 2-input NAND gate open drain Rev. 6 — 28 June 2012 Product data sheet 1. General description The 74AUP1G38 provides the single 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to

74AUP1G386

Abstract: 74AUP1G386GF 74AUP1G386GM 74AUP1G386GW JESD22-A114E
Contextual Info: 74AUP1G386 Low-power 3-input EXCLUSIVE-OR gate Rev. 03 — 2 July 2009 Product data sheet 1. General description The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

74AUP1G38GF

Abstract: 74AUP1G38GM 74AUP1G38GW JESD22-A114E MO-203
Contextual Info: 74AUP1G38 Low-power 2-input NAND gate open drain Rev. 02 — 14 June 2007 Product data sheet 1. General description The 74AUP1G38 provides the single 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to

Contextual Info: 74AUP1G38 Low-power 2-input NAND gate open drain Rev. 5 — 29 November 2011 Product data sheet 1. General description The 74AUP1G38 provides the single 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to

74AUP1G386

Abstract: 74AUP1G386GF 74AUP1G386GM 74AUP1G386GW JESD22-A114E
Contextual Info: 74AUP1G386 Low-power 3-input EXCLUSIVE-OR gate Rev. 02 — 10 January 2008 Product data sheet 1. General description The 74AUP1G386 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Contextual Info: 74AUP1G386 Low-power 3-input EXCLUSIVE-OR gate Rev. 5 — 28 November 2011 Product data sheet 1. General description The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

jesd8-11 jedec

Contextual Info: 74AUP1G386 Low-power 3-input EXCLUSIVE-OR gate Rev. 01 — 29 November 2006 Product data sheet 1. General description The 74AUP1G386 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

74AUP1G38GF

Abstract: 74AUP1G38GM 74AUP1G38GW
Contextual Info: 74AUP1G38 Low-power 2-input NAND gate open drain Rev. 4 — 7 October 2010 Product data sheet 1. General description The 74AUP1G38 provides the single 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to

Contextual Info: 74AUP1G386 Low-power 3-input EXCLUSIVE-OR gate Rev. 6 — 31 July 2012 Product data sheet 1. General description The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

schematic diagram atx Power supply 500w

Abstract: pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS
Contextual Info: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 Digital Signal Processors, iCoupler , iMEMS® and iSensor . . . . . 805, 2707, 2768-2769 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-568 RF Connectors . . . . . . . . . . . . . . . . . . . . . . Pages 454-455

hef4051

Abstract: 74AUP2G34 74LVT1403 74ABT543A 74LV74 74AVCH1T45 74HC590 CBTD3306 NCX2200 74HC40103
Contextual Info: ロジック IC データスイッチ/アナログスイッチ コンパレータ レベルシフタ 汎用ロジック Index 2 ●● P3 NXP ロジック ●● P4 低抵抗アナログスイッチ/データスイッチ ●● P7 コンパレータ ●●