74F273 Search Results

74ABT273

Abstract: 74F273 74FCT273
Contextual Info: 1 Q u a l it y S e m ic o n d u c t o r , I n c . High-Speed CMOS 8-Bit Register with Asynchronous Reset qs 54/74fct 273t FEATURES/BENEFITS DESCRIPTION • Pin and function compatible to the 74F273 74FCT273 and 74ABT273 • Industrial temperature -4 0 °C to 85°C

74F273

Abstract: 74F273A 74F273AD 74F273AN 74F373 74F374 74F377A
Contextual Info: Philips Semiconductors Product specification Octal D flip–flop 74F273A All outputs will be forced Low independently of Clock or Data inputs by a Low voltage level on the MR input. The device is useful for applications where the true output only is required and the CP and

Contextual Info: QSFCT273T, 2273T Q High Speed CMOS 8-Bit Register with Asynchronous Reset qs5474fct273t QS54/74FCT2273T FEATURES/BENEFITS • Pin and function compatible to the 74F273 74FCT273 and 74ABT273 • CMOS power levels: <7.5 mW static • Available in DIP, SOIC, QSOP, ZIP, HQSOP

Contextual Info: QS273T, 2273T Q High-Speed CMOS 8-Bit Register with Asynchronous Reset Q S54/74FCT273T Q S54/74FCT2273T FEATURES/BENEFITS • Pin and function compatible to the 74F273 74FCT 273 and 74FCT273T • CMOS power levels: <7.5 mW static • Available in PDIP, ZIP, SOIC, QSOP, CERDIP

Contextual Info: 273 National Semiconductor 54F/74F273 Octal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D-type flip-flops with in­ dividual D inputs and Q outputs. The common buffered Clock CP and Master Reset (fflR) inputs load and reset

signetics fast 74f273

Abstract: N74F273D
Contextual Info: Signetics FAST 74F273 Flip-Flop Octal D Flip-Flop FAST Products Product Specification FEATURES • High Impedance NPN bas* Inputs for reduced loading 20|iA In Low and High states • Ideal buffer for MOS microproces­ sor or memory • Eight edge-triggered D-type flipflops

74fct2273

Abstract: D5160
Contextual Info: QSFCT273T, 2273T Q High Speed CMOS 8-Bit Register with Asynchronous Reset qs54/74fct 273t qs54/74fct2273t FEATURES/BENEFITS • Pin and function compatible to the 74F273 74FCT273 and 74ABT273 • CMOS power levels: <7.5 mW static • Available in DIP, SOIC, QSOP, ZIP, HQSOP

74F273

Abstract: 74F273PC 74F273SC 74F273SJ 74F373 74F374 74F377 M20D
Contextual Info: Revised September 2000 74F273 Octal D-Type Flip-Flop General Description Features The 74F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

54F273DM

Abstract: 74F273 74F273PC 74F273SC 74F273SJ F373 F374
Contextual Info: 54F 74F273 Octal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously

74F273

Contextual Info: 54F 74F273 Octal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously

74F273N

Abstract: 74F273D 74F273 74F273A 74F273AD 74F273AN 74F373 74F374 74F377 0G521
Contextual Info: PHILIPS INTERNATIONAL 5Ö E ï WË 7110Û5L. 0 Q S 2 1 1 S Philips Semiconductors-Signetics FAST Products Octal D flip-flop 74F273/273A FEATURES DESCRIPTION • High impedance inputs for reduced loading 20[iA in Low and High states The 74F273 has eight edge-triggered D-type

ti 261

Abstract: 74F273
Contextual Info: 54F273,74F273 54F273 Octal D Flip-Flop Literature Number: SNOS182A 54F 74F273 Octal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock CP and Master Reset (MR) inputs load and reset

Contextual Info: S E M IC O N D U C T O R -n 74F273 Octal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D-type flip-flops with in­ dividual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all

74ABT273

Abstract: 74F273 74FCT273 74FCT273 QSOP
Contextual Info: QS54/74FCT273T High-Speed CMOS 8-Bit Register with Asynchronous Reset Q QUALITY SEMICONDUCTOR, INC. QS54/74FCT273T FEATURES/BENEFITS DESCRIPTION • Pin and function compatible to the 74F273 74FCT273 and 74ABT273 • Industrial temperature –40°C to 85°C

74F273N

Abstract: 74F273AD 74F273 74F273A 74F273AN 74F273D 74F373 74F374 74F377
Contextual Info: Produci «pacification Philip» Semiconduclort-Signetfca FAST Products Octal D flip-flop 74F273/273A FEATURES DESCRIPTION • High impedance inputs for reduced loading The 74F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q out­

Contextual Info: N> •Nj CO 59 National ÆÆ Semiconductor 54F/74F273 Octal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D-type flip-flops with in­ dividual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset

74F273N

Abstract: 05091
Contextual Info: Product specification Philips Semiconductors-Signetics FAST Products Octal D flip-flop 74F273/273A FEATURES DESCRIPTION • High impedance inputs for reduced loading The 74F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q out­

Contextual Info: QS273T, 2273T Q High-Speed CMOS 8-Bit Hegister with Asynchronous Reset \V qs54/74fct273t qss4 /7 4 fc t 2273 t FEATURES/BENEFITS • Pin and function compatible to the 74F273 74FCT 273 and 74FCT273T • CMOS power levels: <7.5 mW static • Available in PDIP, ZIP, SOIC, QSOP, CERDIP

Contextual Info: INTEGRATED CIRCUITS 74F273A Octal D flip-flop Product specification 1996 Mar 12 IC15 Data Handbook Philips Semiconductors PHILIPS Philips Semiconductors Product specification Octal D flip-flop 74F273A All outputs will be forced Low independently of Clock or Data inputs

3DD6

Abstract: F374
Contextual Info: 273 54F/74F273 Connection Diagrams O ctal D Flip-Flop ~20|Vcc MR P ~ in o ? O o lZ ht edge-triggered D-type flip-flops w ith individual D The com m on buffered C lo ck CP and M aster Reset reset (clear) all flip-flops sim ultaneously. El. The state of each D input, one setup

74ABT273

Abstract: 74F273 74FCT273 QS32383 QS3383 74fct2273
Contextual Info: QSFCT273T, 2273T Q High Speed CMOS High Speed CMOS 8-BitBus Register with Exchange Asynchronous Reset Switches QS54/74FCT273T QS3383 QS32383 QS54/74FCT2273T FEATURES/BENEFITS • Pin and function compatible to the 74F273 74FCT273 and 74ABT273 • CMOS power levels: <7.5 mW static

Contextual Info: QSFCT2X273T PRELIMINARY Q 16-Bit Register with Asynchronous Reset nchronous R < in QVSOP qs74fct2X273t FEATURES/BENEFITS • Function compatible to the 74F273 74FCT273 and 74ABT273 • CMOS power levels: <15 mW static • Available in 40-Pin QVSOP • Undershoot clamp diodes on all inputs

Contextual Info: 1 6 - B it R e g is t e r w it h Ö q s 7 4 f c t 2X273t A s y n c h ro n o u s R e s e t Q u a l it y S e m ic o n d u c t o r , I n c . in Q V S O P FEATURES/BENEFITS DESCRIPTION • Function compatible to the 74F273, 74FCT273 and 74ABT273 • CMOS power levels: <15mW static

Contextual Info: 273 54F/74F273 Connection Diagrams Octal D Flip-Flop T— r ' - M R p ~ H rS rz a ht edge-triggered D-type flip-flops with individual D The common buffered Clock CP and Master Reset n ^ re s e i (clear) all flip-flops simultaneously. The register is full