74LS279 Search Results

CI 7446

Abstract: CI 74141 cI 74ls47 CI 7447 CI 7448 ci 7445 7-seg ANODE COMMON CI 74LS48 TTL 7446 BCD D147
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T TL 7 1 2 6 3 5 i Ao A RBO a A 2 b A3 e d 1 El e 13 12 11 10 RBI f 9 E 9 15 3 2 4 m l 14 6 m Do MR TTTTTTTT 4 D147 54/74279, 54LS/74LS279 0146 9314, 93L14 D145 9370, 9374 So Qo 7 11 Da $3 V cc iwiEiEi[i3ii«inF5if»i

7475 D flip-flop

Abstract: quad D flip-flop 74175 pin 4 bit shift register 7494 pin diagram latch 74ls574 7477 D latch 74174 shift register 9374 74LS173 4 bit 3 state quad register 74LS279 D flip-flop 74175 pin
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T TL 7 1 2 6 3 5 i Ao A R BO a A 2 b A 3 e d 1 E l RBI e 13 12 11 10 E 9 f 9 15 3 2 4 m l 14 6 m Do M R TTTTTTTT 4 D147 54/74279, 54LS/74LS279 0146 9314, 93L14 D145 9370, 9374 So Qo 7 11 Da $3 V cc iwiEiEi[i3ii«inF5if»i

ci 7475

Abstract: 74175 pin 9374 D147 93L38 74LS75 7477 D latch 74LS77 9370 DA 9370
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L 7 1 2 6 3 5 i Ao A R BO a A 2 b A 3 e d 1 E l RBI e 13 12 11 10 E 9 f 9 15 3 2 4 m l 14 6 m Do So M R TTTTTTTT 4 D147 54/74279, 54LS/74LS279 0146 9314, 93L14 D145 9370, 9374 7 11 Da $3 V cc iwiEiEi[i3ii«inF5if»i

751B03

Abstract: 74ls279 of 74ls279 truth table NOT gate 74 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS279 QUAD SET-RESET LATCH VCC S1 R Q S1 S2 R Q 16 15 14 13 12 11 10 9 QUAD SET-RESET LATCH LOW POWER SCHOTTKY 1 2 3 4 5 6 7 8 R S1 S2 Q R S1 Q GND J SUFFIX CERAMIC CASE 620-09 16 TRUTH TABLE INPUT 1 S1 S2 R OUTPUT Q L L X H H L X L H H L H H L H

74ls characteristics

Abstract: 74LS279 S5427 74279 truth table NOT gate 74 N74279F N74279N N74LS279F N74LS279N S54279F
Contextual Info: PIN CONFIGURATION 54/74279 54LS/74LS279 ORDERING CODE PIN CONF. PACKAGES See Section 9 for further Package and Ordering Information. C O M M ER C IA L RANGES = + 5%; T a = 0 -C to *70"C VCC Plastic DIP Fig. A N74279N • 74LS279N C eram ic DIP Fig. A N74279F

74ls279

Abstract: diode s1 74 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 3S24 S211R
Contextual Info: SN54/74LS279 QUAD SET-RESET LATCH VCC 16 S1 15 R Q 14 13 S1 12 S2 11 R 10 Q 9 QUAD SET-RESET LATCH LOW POWER SCHOTTKY 1 R 2 S1 3 S2 4 Q 5 R 6 S1 7 Q 8 GND J SUFFIX CERAMIC CASE 620-09 16 TRUTH TABLE INPUT 1 S1 S2 R OUTPUT Q L L X H H L X L H H L H H L H

74LS279

Contextual Info: 8 < > MOTOROLA SN54/74LS279 QUAD SET-RESET LATCH V cc s, R Q S2 S, R Q QUAD SET-RESET LATCH LOW POWER SCHOTTKY R S2 Si Q R Si Q f0n GND TRUTH TABLE INPUT J SUFFIX CERAMIC CASE 620-09 1 OUTPUT Si S2 R <Q L L X H H L X L H H L H H L H h H H L No Change N SUFFIX

Contextual Info: LS TTL DN74LS Series 74LS279 74LS279 10741^7*7 Quad S -K Latches • Description P -2 D N 74LS279 contains fo u r R-S flip-flop circuits. ■ Features • • • Low pow er consum ption Pa = 19mW typical Low o u tp u t im pedance Wide operating tem perature range (T a = - 2 0 to +75°C )

7475 d-flip flop

Abstract: 7475 D flip-flop ci 7475 D134 1CN 24 12 74175 74279 9374 FLIP FLOP 7475 Register 7475
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T TL 7 1 2 6 3 5 1 A R BO a A 2 b A 3 e d E l RBI e E 9 f 13 12 11 10 9 15 2 4 14 6 m Do M R TTTTTTTT 4 3 m i l Ao D147 54/74279, 54LS/74LS279 0146 9314, 93L14 D145 9370, 9374 So Qo 7 11 Da $3 V cc iwiEiEi[i3ii«inF5if»i

ci 74174

Abstract: 7475 D flip-flop D flip-flop 74175 pin 74ls175 pin diagram 9374 74116 74175 ttl pin diagram 7477 D latch CI 74LS194 74174
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T TL 7 1 2 6 3 5 1 A R BO a A 2 b A 3 e d E l RBI e E 9 f 13 12 11 10 9 15 2 4 14 6 m Do M R TTTTTTTT 4 3 m i l Ao D147 54/74279, 54LS/74LS279 0146 9314, 93L14 D145 9370, 9374 So Qo 7 11 Da $3 V cc iwiEiEi[i3ii«inF5if»i

74ls279

Abstract: truth table NOT gate 74 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74LS279DC
Contextual Info: SN54/74LS279 QUAD SET-RESET LATCH VCC 16 S1 15 R Q 14 13 S1 12 S2 11 R 10 Q 9 QUAD SET-RESET LATCH LOW POWER SCHOTTKY 1 R 2 S1 3 S2 4 Q 5 R 6 S1 7 Q 8 GND J SUFFIX CERAMIC CASE 620-09 16 TRUTH TABLE INPUT 1 S1 S2 R OUTPUT Q L L X H H L X L H H L H H L H

DN74LS279

Abstract: MA161
Contextual Info: ! 74LS279 LS TTL DN74LS Series 74LS279 Quad S - R L atches • Description P -2 D N 74LS279 contains four R-S flip-flop circuits. ■ Features • • • Low pow er co n sum ption Pd = 19mW typical Low o u tp u t im pedance Wide operating tem perature range (Ta = —20 to +75 C)

Contextual Info: 279 CONNECTION DIAGRAM PINOUT A /V54/74279 ^ , u '/ ° t/54LS/74LS279'?///£7 ' QUAD SET-RESET LATCH ORDERING CODE: See Section 9 PIN PKGS OUT COMMERCIAL GRADE MILITARY GRADE Vcc = +5.0 V ±5%, Ta = 0°C to +70° C Vcc = +5.0 V ±10%, T a = -55°C to +125°C

Contextual Info: M O TO R O LA SN54/74LS279 R R R R FI B TRUTH TABLE H INPUTS h *1 L L X H H LiJ UJ L J ili L H X h UJ LÌJ LiJ J Suffix — Case 62009 Ceramic N Suffix — Case 648*08 (Plastic) L X L H H OUTPUT R L H H L H 10) h H H L No Change QUAD SET-RESET LATCH = LOW Voltage Level

Contextual Info: - TC74HC279AP/AF QUAD S -R LATCH The TC74HC279A is a h ig h speed CMOS QUAD S - R LATCH fa b ric a te d w ith silicon g a te C2MOS technology. It achieves the h ig h speed o peration s im ila r to equivalent L S T T L w hile m a in ta in in g the CMOS low pow er

74LS279PC

Abstract: 74279PC 74LS279D 74279 dip 74LS279P 74LS279DC truth table NOT gate 74 54279DM 54279FM 54LS279DM
Contextual Info: 279 C O N N E C T IO N D IA G R A M P IN O U T A / t / 54/74279 11140 !/5 4 L S /7 4 L S 2 7 9 ; ^ / Q U AD SET-RESET LATCH ÏS ] V cc 23 a ¡a m g n d |T O R D E R IN G C O D E : See S e ctio n 9 PIN PK G S OUT C O M M E R C IA L G R A D E M ILIT A R Y G R A D E

Contextual Info: 5QE D 44^503 G01341Q 5 HITACHI/ L0GIC/ARRAYS/MÉÎ1 0 H IT A C H I S e p t e m b e r , 1985 CMOS GATE ARRAYS i HD61 SERIES DESIGNER'S MANUAL AND PRODUCT SPECIFICATION HITACHI/ LOGIC/ARR'A YS/MEM SQE D • 4 4TLS03 0G13411 4 T -42-11-09 CMOS GATE ARRAYS HD61 SERIES

Contextual Info: TC74HC279AP/AF QUAD S - R LATCH The TC74HC279A is a high speed CMOS QUAD S -R LATCH fabricated with silicon gate C2MOS technology. It achieves the high speed operation sim ilar to equivalent LSTTL while m aintaining the CMOS low power dissipation. Each latch has an independent Q output^ and Set and

Contextual Info: TOSHIBA LOGIC/MEMORY IME D | Ei G T ? a 4 ä 0 0 1 ä 2 ? l b l T-4k-cr?~is TC74HC279P/F QUAD S-R The TC74HC279 is a high speed CMOS QUAD S-R LATCH fabricated with silicon gate C2M0S technology.

74LS279 equivalent

Abstract: 16PIN 74LS279 TC74HC279AF TC74HC279AP
Contextual Info: TOSHIBA TC74HC279AP/AF TO SH IBA CM OS D IG ITAL INTEGRATED CIRCUIT SILICON M ONOLITHIC TC74HC279AP, TC74HC279AF QUAD S - R LATCH The TC74HC279A is a high speed CMOS QUAD S - R LATCH fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent

CI 7474

Abstract: CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 TTL 74ls76 fairchild 9024 ci 74LS74 74ls107
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 ui 9 D UJ 5 -=pi (3 J Q 2 — J SD 0 CP Z o (3 11 4 K Ä 0 Co “LT in > _6 12 CP 3 -0 14 K Co ° 7 o-i- CP 13 —c K Cd °

C350AVB

Abstract: full adder using Multiplexer IC 74150 74LS382 74ls69 T2D 7N IC 74ls147 pin details 74LS396 MB652xxx 651XX 74LS86 full adder
Contextual Info: FUJITSU MICROELECTRONICS F U JIT S U wmmm 7flC D B 37MT7bH □D03c]4b 3 • JZ CMOS Gate Array GENERAL INFORMATION The Fujitsu CM O S gate array fam ily consists of tw en tyeight device types which are fabricated w ith advanced silicon gate CMOS technology. And more than 14 devices

74hc279

Contextual Info: r z j SG S TH O M SO N *7# fflDMO IIL[i g»)RDO i M54HC279 M74HC279 QUAD S - R LATCH • HIGH SPEED tPD = 13 ns (TYP.) at VCc = 5V ■ LOW POWER DISSIPATION lCc = 2 /iA (MAX.) at TA = 25°C ■ HIGH NOISE IMMUNITY V NIH = V n i l = 28 % VCc (MIN.) ■ OUTPUT DRIVE CAPABILITY

TC74HC279AP

Abstract: 74LS279 TC74HC279AF of 74ls279 74LS279 equivalent
Contextual Info: TC74HC279AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC279AP,TC74HC279AF Quad S - R Latch The TC74HC279A is a high speed CMOS QUAD S-R LATCH fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent