74ACT74 Search Results

74ACT74 equivalent

Abstract: 74ACT74
Contextual Info: S G S -T H O M S O N 74ACT74 DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR . HIGHSPEED: fMAX =250 MHz TYP. at Vcc =5V . LOW POWER DISSIPATION: Ice = 4 |xA (MAX.) at T a = 25 °C . COMPATIBLE WITH TTL OUTPUTS Vih = 2V (MIN), V il = 0.8V (MAX) . 50i2 TRANSMISSION LINE DRIVING

Contextual Info: Novem ber Revised D ecem ber 1998 S E M I C O N D U C T O R TM 74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop General Description A synchronous Inputs: T h e AC /AC T74 is a dual D-type flip-flop with Asynchronous C lear and S e t inputs and com plem entary Q, Q outputs.

lm 4572 SMD 8 PIN

Contextual Info: February 1993 54AC/74AC74 • 54ACT/74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop General Description The ’A C /’AC T74 is a dual D -type flip-flo p w ith A syn ch ro ­ nous C lear and Set inputs and com plem entary Q, Q o ut­ puts. Inform ation at th e input is transferred to th e o utputs on

Contextual Info: [ /Title CD74 AC74, CD74 ACT74 /Subject (Dual DType FlipFlop with Set and Reset PositiveEdgeTriggered) /Autho r () /Keywords (Harris Semiconductor, Advan ced CMOS , Harris Semiconductor, Advan CD54/74AC74, CD54/74ACT74 Data sheet acquired from Harris Semiconductor

74AC74

Abstract: 74AC74MTC 74AC74SC 74AC74SJ 74ACT74 ACT74 M14A M14D MTC14
Contextual Info: A S E I R M C H N ovem ber 1988 D • Revised D ecem kber iOQo 1998 I L D ¡C O N D U C T O R TM 74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: T h e AC/ACT74 is a dual D-1ype flip-flop with Asynchronous

Contextual Info: Semiconductor 54AC/74AC74 • 54ACT/74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop General Description The 'A C /’ACT74 is a dual D-type flip-flop with Asynchro­ nous Clear and Set inputs and complementary Q, Q out­ puts. Information at the input is transferred to the outputs on

Contextual Info: MC74AC74 74ACT74 Dual DĆType Positive EdgeĆTriggered FlipĆFlop The MC74AC74/74ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q,Q outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage

smd AC74

Abstract: national 74act74 54ACT 74AC 74AC74 74ACT74 AC74 ACT74 C1995 B50 diode smd
Contextual Info: 54AC 74AC74  54ACT 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop General Description The ’AC ’ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q Q outputs Information at the input is transferred to the outputs on

Y0803

Abstract: U0801B IC LM7805 N1 Y10 pin diagram of IC LM7805 C0801 STI3400 U0101 U0604 plx9060
Contextual Info: Q CL 7 D PR 3 4 14 2 U?A Q 5 CLK 6 {Value} 1 1 2 3 4 5 6 SPARE GATES: 8 ECN HISTORY DESCRIPTION REV 2 -ADD CDREQ DATE APPROVAL 10/24/95 U0101 PU0101 A PU0102 PU0103 12 11 D U0801B 9 Q CLK 8 Q 74ACT74 13 20V8C DIP 22 21 20 19 18 17 16 15 CL O1 IO2 IO3 IO4 IO5

u0101

Abstract: u0801b 74ACT74
Contextual Info: 1 2 3 4 5 6 SPARE GATES: 8 ECN HISTORY DESCRIPTION REV 2 -ADD CDREQ DATE APPROVAL 10/24/95 U0101 PU0101 A PU0102 PU0103 12 11 D U0801B 9 Q CLK 8 Q 74ACT74 13 20V8C DIP 22 21 20 19 18 17 16 15 CL O1 IO2 IO3 IO4 IO5 IO6 IO7 O8 PR I1 I2 I3 I4 I5 I6 I7 I8 I9 I10

ac74g

Abstract: ACT74G 74AC ACT74 MC74AC74 MC74AC74N MC74ACT74 MC74ACT74N
Contextual Info: MC74AC74, 74ACT74 Dual D−Type Positive Edge−Triggered Flip−Flop The MC74AC74/74ACT74 is a dual D−type flip−flop with Asynchronous Clear and Set inputs and complementary Q,Q outputs. Information at the input is transferred to the outputs on the

Contextual Info: Technical Data CD54/74AC74 CD54/74ACT74 Dual D-type Flip-Flop with Set and Reset Positive-Edge-Triggered Type Features: • B uffered inputs m Typical propagation delay: 4.9 ns @ l/cc = 5 V, TA = 25° C, C l = 50 pF FUNCTIONAL DIAGRAM & TERMINAL ASSIGNMENT

Y0803

Abstract: R0801 U0801A Y0802 PU0806 C0801 STI3400 R0806 U0802 R0803
Contextual Info: 1 2 1 7 Y0801 NC VCC GND OUT 3 14 4 5 6 7 8 VCC 8 1 CLK50R 50 MHz R0801 2 CLK50 FOR STI3400 33 A 4 A CLK25R~ 1 PU0801 4 3 D PR 2 CLK25A FOR PCI9060, FIFO 33 U0801A Q R0802 2 5 CLK25R 1 R0803 2 CLK25B FOR MACHS 33 CLK CL Q 2,4,9 3 6 74ACT74 1 PU0802 1 7 B VCC

16V8-10

Abstract: semiconductor ad 5.9 u0304 R0801 74ACT74 LD11 LD12 U0801A LA17 MXA0 A10
Contextual Info: ECN HISTORY |LINK |N2.SCH |N3.SCH |N4.SCH |N5.SCH |N6.SCH |N7.SCH SPARE GATES: DESCRIPTION DATE REV 1 - 01/24/96 REV 2 -CHANGED DRMMUX 2/17/96 APPROVAL PU0101 1 PU0102 PU0103 12 11 D P R U0303B Q 9 CLK C L 1 3 Q 8 74ACT74 PU0104 APPROVALS DATE PLX TECHNOLOGY

3vf5

Contextual Info: Technical D a ta _ _ m - Hi 3D54/74AC74 DD54/74ACT74 IAXIMUM RATINGS, A bsolute-M axim um Values: >C SUPPLY-VOLTAGE Vcc .-0.5 to 6 V

74AC74PC

Abstract: 74AC74 74AC74MTC 74AC74SC 74AC74SJ 74ACT74 74ACT74SC 74ACT74SJ ACT74 33DN
Contextual Info: Revised November 1999 74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop General Description Features The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q, Q outputs. Information at the input is transferred to the outputs on the

ACT74

Abstract: MC74AC74 MC74AC74D MC74AC74DR2 MC74AC74N MC74ACT74 MC74ACT74D MC74ACT74DR2 MC74ACT74N
Contextual Info: MC74AC74, 74ACT74 Dual D−Type Positive Edge−Triggered Flip−Flop The MC74AC74/74ACT74 is a dual D−type flip−flop with Asynchronous Clear and Set inputs and complementary Q,Q outputs. Information at the input is transferred to the outputs on the

motorola act74

Abstract: act74
Contextual Info: M MOTOROLA M C74AC74 M 74ACT74 Product Preview Dual D-Type Positive Edge-Triggered Flip-Flop DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC74AC74/74ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and com plem entary Q, Q) outputs. Information at the input is trans­

motorola act74

Abstract: 74AC ACT74 MC74AC74 MC74ACT74
Contextual Info: MC74AC74 74ACT74 Dual DĆType Positive EdgeĆTriggered FlipĆFlop The MC74AC74/74ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q,Q outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering

Contextual Info: [ /Title CD74 AC74, CD74 ACT74 /Subject (Dual DType FlipFlop with Set and Reset PositiveEdgeTriggered) /Autho r () /Keywords (Harris Semiconductor, Advan ced CMOS , Harris Semiconductor, Advan CD54/74AC74, CD54/74ACT74 Data sheet acquired from Harris Semiconductor

LM358 vs LM741

Abstract: LM607CN LM324 vs LM741 LM337 TO-92 L308A L1117-3.3 LM2980 LM741 vs. LM324 m6 sot-23 pinout datasheet of IC 74LS90
Contextual Info: National Semiconductor to Texas Instruments Cross-Reference National Semiconductor GPN 74AC74 74AC74 74ACT00 74ACT374 74ACT374 74ACT374 74ACT374 74ACT374 74ACT374 74ACT374 74ACT374 74ACT74 74ACT74 74F109 74F109 74F151A 74F151A 74F151A 74F153 74F153 74F153

ACT74

Abstract: 54ACT 74AC
Contextual Info: AC74 • ACT74 54AC/74AC74 • 54ACT/74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop Description Connection Diagrams The ’AC/’ACT74 is a duat D-type flip -flo p w ith A synchronous C lear and Set in pu ts and com plem entary Q, Ü ou tputs. Inform a tion at the

AC00

Abstract: AC74 ACT74 CD54AC74F3A CD74AC74E CD74AC74EX D112CP
Contextual Info: [ /Title CD74 AC74, CD74 ACT74 /Subject (Dual DType FlipFlop with Set and Reset PositiveEdgeTriggered) /Autho r () /Keywords (Harris Semiconductor, Advan ced CMOS , Harris Semiconductor, Advan CD54/74AC74, CD54/74ACT74 Data sheet acquired from Harris Semiconductor

74AC

Abstract: ACT74 MC74AC74 MC74AC74N MC74AC74NG MC74ACT74 MC74ACT74DG mc74ac74dr2g MC74ACT74DR2G MC74ACT74N
Contextual Info: MC74AC74, 74ACT74 Dual D−Type Positive Edge−Triggered Flip−Flop The MC74AC74/74ACT74 is a dual D−type flip−flop with Asynchronous Clear and Set inputs and complementary Q,Q outputs. Information at the input is transferred to the outputs on the