74LS Search Results

74283 IC pin diagram

Abstract: IC 74283 74283 IC 8 bit pin diagram
Contextual Info: SN54283, SN54LS283, SN54S283, SN74283, SN 74LS283, SN74S283 4 BIT BINARY FU LL AD DERS W ITH FA S T CARRY OCTOBEH 1976 - REVISED MARCH 1988 S N 5 4 2 8 3 , S N 5 4 L S 2 8 3 . . . J OR W PAC KA G E S N 5 4 S 2 8 3 . . . J P AC K A G E S N 7 4 2 8 3 . . . N P AC K A G E

74ls303

Abstract: 7459 IC TTL sn 7458 IC 7458 64LS 84ls IC 7459 IC 74283 sn 7457
Contextual Info: TTL MSI . TYPES SNS41S3I3. 74LS363 DUAL 4-LINE-TO-l-LHftf DATA SILECTOit^MULIU>LEXERS WITH 3-STATE OUTPUTS B U LLETIN NO. DL-S 781246J , O CTO BER 1976 SN 54LS 353 . . . J O R W P A C K A G E SN 74LS 353 . . . J O R N P A C K A G E T O P V |E W Inverting Versions of SN54LS253, 74LS2S3

74LS166A

Abstract: 54ls166a 54LS166
Contextual Info: SN54166, SN 54LS166A, SN74166. SN 74LS166A PARALLEL LOAD 8-BIT SHIFT REGISTERS OCTOBER 1976 - REVISED MARCH 1988 S N 54166, S N 54LS 166A . . . J OR W PACKAGE S N 7416 6 . . . N PACKAGE S N 74LS 166A . . . D OR N PACKAGE • Synchronous Load • Direct Overriding Clear

IC 74LS153

Abstract: 74153 mux cd 74153 ic 74153 IC - 74LS153 74LS153 8 to 1 mux 74LS153 74153 74s153 2C011
Contextual Info: SN54153, SN 54LS153, SN 54S1S3 S N 74153, SN 74LS153, SN 74S153 DUAL 4 LINE TO 1-LINE DATA SELECTORSfM ULTIPLEXERS D E C E M B ER 1972 - R E V IS E D M A R C H 19B8 Permits Multiplexing from N lines to 1 line S N 54153, SN 5 4 LS1 5 3 , SN 5 4 S1 5 3 . . . J OR W

LS 7475

Abstract: C4408
Contextual Info: SN5475, SN5477, SN54LS75, SN54LS77. SN7475, 74LS75 4 BIT BISTABLE LATCHES MAR CH 1 9 7 4 - each latch (TOP VIEW) OUTPUTS INPUTS REVISED M A R C H 1 9 8 8 SN 5475 , SN 54LS75 . . . J OR W PACKAGE S N 7475 . . . N PACKAGE SN 74LS 75 . . . D O R N PACKAGE

74LS266M

Abstract: LS266 74L826 74LS266
Contextual Info: TYPES SN54LS286, 74LS266 QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES WITH OPEN-COUECTOR OUTPUTS TTL MSI B U L L E T IN NO. D L-S 7611843, D E C E M B E R 1 9 7 2 - R E V IS E O O C T O B E R 1B7S S N 6 4LS 266 . . . J O R W P A C K A G E SN 74LS266. . . J OR N P A C K A S E

SN54LS654

Contextual Info: TYPES SN54LS651 THRU SN54LS654 74LS651 THRU 74LS654 OCTAL BUS TRANSCEIVERS AND REGISTERS 02637, JA N U A R Y ' • Bus Transceivers/Registers 19 81 - R E V IS E D DECEMBER 1983 S N 54LS ' . . . JT PACKAGE S N 74LS ' . . . D W , JT OR N T PACKAG E Independent Registers and Enables for A and

54LS466

Abstract: 74LS467 74LS465 74LS468 74ls46 81LS98 74ls466
Contextual Info: SN54LS465 THRU SN54LS468, 74LS465 THRU 74LS468 OC TAL BU FFERS W ITH 3 S T A T E OUTPUTS D 2 6 3 1 , JA N U A R Y 1981 - SN 54LS465 AND SN 54LS466 . . . J PACKAGE SN 74LS465 AND SN 74LS466 . . . DW OR N PACKAGE TOP VIEW! G1 A1 • 3-State Outputs Rated at lo L o f 12 m A and

Contextual Info: SN54LS242, SN54LS243, 74LS242, 74LS243 QUADRUPLE BUS TRANSCEIVERS APHIL 1985 —REVISED MARCH 198B • T w o -W a y Asynchronous C om m unication B etw een D ata Buses • P N P Inputs Reduce D -C Loading SN 54LS 242, SN 54LS 243 . . . J OR W PACKAGE SN 74LS 242. SN 74LS243 . . . D OR N PACKAGE

74ls597

Abstract: 74LS59B
Contextual Info: SN54LS597, SN 54LS598, 74LS597. SN 74LS59B 8 BIT SHIFT REGISTERS WITH INPUT LATCHES 02635 8-Bit Parallel Storage Register Inputs 'LS597J JA N U A R Y 1981 - REVISED M AR C H 1988 S N 5 4 L S 5 9 7 . . . J OR W P AC KA G E S N 7 4 L S 5 9 7 . . . N P AC KA G E

s433

Abstract: 74LS33 IC 7433
Contextual Info: SN 5433, SN 54LS33, SN 7433, SN 74 LS3 3 QUADRUPLE 2 INPUT POSITIVE-NOR BUFFERS WITH OPEN COLLECTOR OUTPUTS DECEMBER 1983-REVISED MARCH 19B8 S N 5 4 3 3 , S N 5 4 L S 3 3 . . J OR W PAC KA G E S N 7433 . . N P AC KA G E SN 74LS33 . . D OR N P AC KA G E TO P V IE W

N74s174

Contextual Info: S N 5 4 1 74 , S N 5 4 1 75 , S N 5 4 L S 17 4 , S N 5 4 L S 17 5 , S N 5 4 S 1 7 4 , S N 5 4 S 175 , SN 74 174 , SN 74 175 , SN 74 LS 174, SN 74LS175, S N 74 S 174, SN74S175 HEX/QUADRUPLE D-TYPE FLIP FLOPS WITH CLEAR D E C E M B E R 1 9 7 2 - R E V l S E D M A R C H 1 9 8 8

74ls610

Abstract: D2549 74LS612 SN74LS610 TMS9900 LS610
Contextual Info: SN54LS610, SN54LS612, 74LS610 THRU 74LS613 MEMORY MAPPERS D2549, JANUARY 1 98 1 -REVISED MARCH 1988 • Expands 4 Address Lines to 12 Address Lines S N 5 4 L S ' . . . J D P AC K A G E 74LS' . JD OR N P AC K A G E TO P VIE W • Output Latches Provided on 'LS610 and

SN74LS383

Contextual Info: TYPES SN54LS363. SN54LS364. 74LS363, SN741S364 OCTAL D-TYPE TRANSPARUT IATCMESAND ED6E-TRI6CEBED FUP-FlOPS TTL MSI BULLETIN HO. OL-& 7*11*6«, OCTOBiR 107« • SNMLS363 . . . J PACKAGE 74LS383 . . . J OR N PACKAGE TOP VIEW High VOH •• ■3.65 V Min ( 74LS')

IC 7428

Abstract: 74LS28 TTL 7428
Contextual Info: SN 5428, S N 54LS28, SN 7428, SN 74LS28 QUADRUPLE 2-INPUT POSITIVE NOR BUFFERS DECEM BER • Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs SN 5428, SN54LS28 S N 7428. SN 74LS28 .

ls125a

Abstract: ls126A 74LS126A 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS125A SN54/74LS126A QUAD 3-STATE BUFFERS VCC E D O E D O 14 13 12 11 10 9 8 QUAD 3-STATE BUFFERS LOW POWER SCHOTTKY 1 2 3 E D O 4 5 6 7 E D O GND LS125A J SUFFIX CERAMIC CASE 632-08 VCC E D O E D O 14 13 12 11 10 9 8 14 1 N SUFFIX PLASTIC CASE 646-06

pin DIAGRAM OF IC 74ls32

Abstract: cmos 74ls32 of IC 74LS32 2099A 74LS32 power dissipation IC 74LS32 74ls32 equivalent LC74HC32M 74LS32 pinout
Contextual Info: SANYO SEMICONDUCTOR CORP 1HE D I 7Ti7Q7Li □ □QSt.47 û T ~ -^ V 2 .1 CMOS High-Speed Standard Logic LC74HC Series 3034A Quad 2-Input OR Gate £2099A Features • The LC74HC32M consists of 4 identical 2*input OR gates. • Uses CMOS silicon gate process technology to achieve operating speeds similar to LS.TTL 74LS32 w ith the

Contextual Info: 74LS295B Signetics Shift Register 4-Bit Shift Register With 3-State Outputs Product Specification Logic Products FEATURES • 4-bit parallel load shift register • Independent 3-State buffer outputs • See '395 for serial expansion and Master Reset version

Contextual Info: SA NY O SEMICONDUCTOR 15E D I CORP 7 clci7G7b O O O S b O D LC74HC02 3003A *• v ’ ~ CM O S High-Speed Standard Logic LC74HC Series Quad 2-Input N O R Gate 16958 Features The LC74HC02 consists of 4 identical 2-input NOR gates. Uses CMOS silicon gate process technology to achieve operating speeds similar to LS-TTL 74LS02 with the

Contextual Info: Separate clock and preset Inputs BLOCK DIAGRAM (Each Flip-Flop) SPEED/PACKAGE AVAILABILITY 54LS F,W 54S A,F,W PIN CONFIGURATION 74LS A,F 74S A,F A ,F ,W DESCRIPTION PA C K A G E CLOCK 1 ^ A low level at the preset input sets the Q output high regardless of the levels at the

74LS169A

Abstract: 74LS168A 74S168A S168A 74S169
Contextual Info: 74LS168A, 74LS169A, S168A, S169A Signetics 4-Bit Bidirectional Counters 4-Bit Up/Down Synchronous Counter Product Specification Logic Products FEATURES • Synchronous counting and loading • Up/down counting • Modulo 16 binary counter — '169A • BCD decade counter — ' 168A

IC AND GATE 7408

Abstract: TTL 7408 IC AND GATE 7408 pin configuration LM 7408 IC 7408 TTL 7408 AND propagation delay function IC 7408 74LS08 pin configuration IC PIN CONFIGURATION OF 74LS08 IC 7408 and function
Contextual Info: Sjgnetics I 7408, LS08, S08 Gates Quad Two-Input AND Gate Product Specification Logic Products TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT TOTAL 7408 16ns 16mA 74LS08 9ns 3.4mA 74S08 5ns 25mA ORDERING CODE COMMERCIAL RANGE Vcc = 5V ±5%; TA = 0°C to +70“C

74LS90 pin configuration

Abstract: configuration 74ls90
Contextual Info: SPEED/PACKAGE AVAILABILITY 54 F,W S4LS F,W BLOCK DIAGRAM 54LS/74LS PIN CONFIGURATION 74 A,F 74LS A,F DESCRIPTION This monolithic counter contains four mas­ ter-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the

N74LS642N

Abstract: ls642
Contextual Info: Sìgnetics 74LS641, LS642, 74LS641-1, LS642-1 Transceivers Octal Bus Transceiver Open Collector Product Specification Logic Products FEATURES • Octal bidirectional bus interface • Open Collector Outputs — 'LS641, non-inverting — 'LS642, inverting