74LS SERIES DATA BOOK Search Results

W3B4

Contextual Info: SPEED/PACKAGE AVAILABILITY 54 F,W 54LS F.W PIN CONFIGURATION 74 B 74LS B B,F,W PACKAGE T J- °,[7 DESCRIPTION The register file is organized as 4 words of 4 bits each and separate on-chip decoding is provided for addressing the four word locations to either write-in or retrieve data. This

74LS115

Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
Contextual Info: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25

S9301

Abstract: S-9301 74195 pin configuration 74195 pin diagram N9300B HA2E 74195 function table N9301
Contextual Info: SPEED/PACKAQE AVAILABILITY 54LS F,W FUNCTION TABLE PIN CONFIGURATION EACH GATE 74LS A INPUTS A B L L H H L H L H OUTPUT L H H L H = high level L = low level SWITCHING CHARACTERISTICS PARAMETER* *PLH *PHL 'PLH *PHL FROM (INPUT) Vc c = 5V, TA = 25"C LIMITS

LS07

Abstract: SN54LS17 74LS07 54LS07
Contextual Info: TEXAS INSTR LOGIC B1E D 0^1723 OGâôlbM 7 • T I I 3 SN54LS07, SN54LS17, SN74LS07, SN74LS17 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS D3517, MAY 1990 _ T - H 3 - I 5 - O Q SN54LS07, SN54LS17 . J PACKAGE SN74LS07, SN74LS17 . . . D OR N PACKAGE

sn74ls173an

Contextual Info: SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 D D D TYPE TYPICAL PROPAGATION DELAY TIME MAXIMUM CLOCK FREQUENCY ’173 23 ns 35 MHz ’LS173A 18 ns 50 MHz description SN54173, SN54LS173A . . . J OR W PACKAGE

Difference between LS, HC, HCT devices

Abstract: TC4S69F Small Signal Zener Diod difference between 74ls and 74hc ic TC74HC04
Contextual Info: C2MOS Logic TC74HC/HCT Series 9. Precautions in Designing Circuits 9-1 Input Processing 1 Processing of unused gate Inputs of CMOS IC have such a high impedance that the logic level becomes undefined under open conditions. If the input is at an intermediate level, the P-channel and Nchannel transistors both turn on, and excessive supply

8002301FA

Contextual Info: SN54LS257B, SN54LS258B, SN54S257, SN54S258 SN74LS257B, SN74LS258B, SN74S257, SN74S258 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS SDLS148 – OCTOBER 1976 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.

register SN74LS173A

Abstract: SN54173 SN54LS173A SN74173 SN74LS173A
Contextual Info: SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 D D D TYPE TYPICAL PROPAGATION DELAY TIME MAXIMUM CLOCK FREQUENCY ’173 23 ns 35 MHz ’LS173A 18 ns 50 MHz description SN54173, SN54LS173A . . . J OR W PACKAGE

LS147

Abstract: LS148 SN74148
Contextual Info: Product Folder Obsolete : SN74148, 8-Line To 3-Line Priority Encoders Home | Company Info | Employment | TI Global | Contact Us | Site Map • Advanced Search PRODUCT FOLDER | PRODUCT INFO: FEATURES | DESCRIPTION | DATASHEETS | PRICING/AVAILABILITY/PKG |

Contextual Info: SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 D D D TYPE TYPICAL PROPAGATION DELAY TIME MAXIMUM CLOCK FREQUENCY ’173 23 ns 35 MHz ’LS173A 18 ns 50 MHz description SN54173, SN54LS173A . . . J OR W PACKAGE

Contextual Info: SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 D D D TYPE TYPICAL PROPAGATION DELAY TIME MAXIMUM CLOCK FREQUENCY ’173 23 ns 35 MHz ’LS173A 18 ns 50 MHz description SN54173, SN54LS173A . . . J OR W PACKAGE

register SN74LS173A

Abstract: SN54173 SN54LS173A SN74173 SN74LS173A SNJ54173J
Contextual Info: SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 D D D TYPE TYPICAL PROPAGATION DELAY TIME MAXIMUM CLOCK FREQUENCY ’173 23 ns 35 MHz ’LS173A 18 ns 50 MHz description SN54173, SN54LS173A . . . J OR W PACKAGE

SN54173

Abstract: SN54LS173A SN74173 SN74LS173A
Contextual Info: SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 D D D TYPE TYPICAL PROPAGATION DELAY TIME MAXIMUM CLOCK FREQUENCY ’173 23 ns 35 MHz ’LS173A 18 ns 50 MHz description SN54173, SN54LS173A . . . J OR W PACKAGE

Contextual Info: SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 D D D TYPE TYPICAL PROPAGATION DELAY TIME MAXIMUM CLOCK FREQUENCY ’173 23 ns 35 MHz ’LS173A 18 ns 50 MHz description SN54173, SN54LS173A . . . J OR W PACKAGE

Contextual Info: SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 D D D TYPE TYPICAL PROPAGATION DELAY TIME MAXIMUM CLOCK FREQUENCY ’173 23 ns 35 MHz ’LS173A 18 ns 50 MHz description SN54173, SN54LS173A . . . J OR W PACKAGE

Contextual Info: SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 D D D TYPE TYPICAL PROPAGATION DELAY TIME MAXIMUM CLOCK FREQUENCY ’173 23 ns 35 MHz ’LS173A 18 ns 50 MHz description SN54173, SN54LS173A . . . J OR W PACKAGE

74LS TTL

Abstract: catalog 74ls
Contextual Info: SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 D D D TYPE TYPICAL PROPAGATION DELAY TIME MAXIMUM CLOCK FREQUENCY ’173 23 ns 35 MHz ’LS173A 18 ns 50 MHz description SN54173, SN54LS173A . . . J OR W PACKAGE

Contextual Info: SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 D D D TYPE TYPICAL PROPAGATION DELAY TIME MAXIMUM CLOCK FREQUENCY ’173 23 ns 35 MHz ’LS173A 18 ns 50 MHz description SN54173, SN54LS173A . . . J OR W PACKAGE

Contextual Info: SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 D D D TYPE TYPICAL PROPAGATION DELAY TIME MAXIMUM CLOCK FREQUENCY ’173 23 ns 35 MHz ’LS173A 18 ns 50 MHz description SN54173, SN54LS173A . . . J OR W PACKAGE

SNJ54S283J

Contextual Info: SN54283, SN54LS283, SN54S283, SN74283, SN74LS283, SN74S283 4ĆBIT BINARY FULL ADDERS WITH FAST CARRY SDLS095A – OCTOBER 1976 – REVISED MARCH 1988 description Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.

LS196

Contextual Info: IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold

SNJ54LS283J

Contextual Info: SN54283, SN54LS283, SN54S283, SN74283, SN74LS283, SN74S283 4ĆBIT BINARY FULL ADDERS WITH FAST CARRY SDLS095A – OCTOBER 1976 – REVISED MARCH 1988 description Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.

Contextual Info: SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 D D D TYPE TYPICAL PROPAGATION DELAY TIME MAXIMUM CLOCK FREQUENCY ’173 23 ns 35 MHz ’LS173A 18 ns 50 MHz description SN54173, SN54LS173A . . . J OR W PACKAGE

register SN74LS173A

Abstract: SN54173 SN54LS173A SN74173 SN74LS173A
Contextual Info: SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 D D D TYPE TYPICAL PROPAGATION DELAY TIME MAXIMUM CLOCK FREQUENCY ’173 23 ns 35 MHz ’LS173A 18 ns 50 MHz description SN54173, SN54LS173A . . . J OR W PACKAGE