74LS3 Search Results

s433

Abstract: 74LS33 IC 7433
Contextual Info: SN 5433, SN 54LS33, SN 7433, SN 74 LS3 3 QUADRUPLE 2 INPUT POSITIVE-NOR BUFFERS WITH OPEN COLLECTOR OUTPUTS DECEMBER 1983-REVISED MARCH 19B8 S N 5 4 3 3 , S N 5 4 L S 3 3 . . J OR W PAC KA G E S N 7433 . . N P AC KA G E SN 74LS33 . . D OR N P AC KA G E TO P V IE W

4LS395

Contextual Info: SN54LS395A, 74LS395A 4-BIT CASCADABLE SHIFT REGISTERS WITH 3-STATE OUTPUTS OCTOBER 1976 - REVISED MARCH 1960 Three-State, 4 Bit. Cascadable, Parallel-ln, Parallel-Out Registers S N 5 4LS 3 95 A . . . J OR W PA CK A G E SN 74LS39SA . . . D OR N PA CKAGE T O P V IE W !

pin DIAGRAM OF IC 74ls32

Abstract: cmos 74ls32 of IC 74LS32 2099A 74LS32 power dissipation IC 74LS32 74ls32 equivalent LC74HC32M 74LS32 pinout
Contextual Info: SANYO SEMICONDUCTOR CORP 1HE D I 7Ti7Q7Li □ □QSt.47 û T ~ -^ V 2 .1 CMOS High-Speed Standard Logic LC74HC Series 3034A Quad 2-Input OR Gate £2099A Features • The LC74HC32M consists of 4 identical 2*input OR gates. • Uses CMOS silicon gate process technology to achieve operating speeds similar to LS.TTL 74LS32 w ith the

Contextual Info: 74LS377 S ignetics Flip-Flop Octal D Flip-Flop With Clock Enable Product Specification Logic Products FEATURES • Ideal for addressable register applications • Clock Enable for address and data synchronization applications • Eight edge-triggered D flip-flops

74LS395A

Contextual Info: Signetics 74LS395A Shift Register 4-Bit Cascadable Shift Register With 3-State Outputs Product Specification Logic Products FEATURES TYPE • 4-blt parallel load shift register • Independent 3-state buffer outputs • Separate Q3 output for serial expansion

Contextual Info: 60SHSZUUV Am 25LS09 Quad Two-Input, High-Speed Register DISTINCTIVE CHARACTERISTICS • • • 4-bit register accepts data from one-of-two 4-bit input fields Edge triggered clock action Second sourced by T.l. as 54LS/74LS399 Am25LS D.C. parameters including:

DN74LS395A

Abstract: MA161
Contextual Info: 74LS395A LS TTL DN74LS Series 74LS395A 4 -b it Cascadable Shift R egisters with 3 -sta te Outputs • D escription P -2 D N 74LS395A is a 4-bit serial/parallel input to serial/parallel o u tp u t shift register w ith 3-state outputs. ■ Features •

74LS399

Contextual Info: Arrt25LS09 Am25LS09 Quad Two-Input, High-Speed Register DISTINCTIVE CHARACTERISTICS • • • 4-bit register accepts data from one-of-two 4-bit input fields Edge triggered clock action Second sourced by T.l. as 54LS/74LS399 Am25LS D.C. parameters including:

BU 11A

Abstract: 54LS352DM 54LS352FM 74LS352DC 74LS352FC 74LS352PC
Contextual Info: 352 C O N N E C T IO N D IA G R A M P IN O U T A 54LS/74LS352 Ö/O (o DUAL 4-IN PU T MULTIPLEXER D E S C R IP T IO N — T he ’352 is a ve ry h ig h speed dual 4 -in p u t m u ltip le x e r w ith C o m m o n S e le ct in p u ts and in d iv id u a l Enable in p u ts fo r each se ctio n. t can

DN74LS366A

Abstract: MA161
Contextual Info: 74LS366A LS TTL DN74LS Series 74LS366A 74 LSSfeCPr Hex B u s D riv e r s with 3 - s t a * e Outputs • Description D N 74LS366A P -2 c o n t a in s s ix 3 -state o u tp u t^ in v e rte r b u ffe r c ir c u it s w ith c o m m o n o u tp u t - c o n t r o l in p u ts G i a n d G 2 .

74LSOO

Abstract: HD74LS390 Hitachi Scans-001
Contextual Info: • Dual Decade Counters I BLOCK DIAGRAM {'A This circuit contains eight master-slave flip-flops and ad­ ditional gating to implement two individual four-bit counters. The H D 74LS390 incorporates dual divide-by-two and divideby-five counters, which can be used to implement cycle

741s

Abstract: CI 741S DN74LS30 MA161
Contextual Info: LS TTLDN74LS Series 74LS30 74LS30 £>to 7a LS 30 8 - input P o sitiv e N AN D Gates B Description P-1 DN 74LS30 contains one 8-input positive isolation NAND gate circuit. • Features • • • • Low pow er consum ption Pd = 2.5m W typical High speed ( t pd = 1 In s typical)

54LS378DM

Abstract: 54LS378FM 74LS378DC 74LS378FC 74LS378PC 6bit register
Contextual Info: 378 C O N N E C T IO N D IA G R A M P IN O U T A / / • b ^ V 54LS/74LS378 P A R A L LE L D REGISTER \ With Enable 1 TjOvcc iE QoE Ï Do [3 Ü lD s s ]Q 5 D i[4 là ] 04 Q i[| T 2I Q d2 [| îï] “3 0 2 |T ÏÔ ]0 3 GNO [ T J }C P D E S C R IP T IO N — T h e ’378 is a 6 -b it reg iste r w ith a b u ffe re d co m m o n enable.

74LS386

Abstract: SN54/74LS386 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74LS386DC
Contextual Info: SN54/74LS386 QUAD 2-INPUT EXCLUSIVE-OR GATE QUAD 2-INPUT EXCLUSIVE-OR GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 14 1 1 2 3 4 5 6 7 GND N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION

751A-02

Abstract: TTL 74ls30 FAST AND LS TTL motorola ceramic dual in-line case 74ls30 datasheet
Contextual Info: SN54/74LS30 8-INPUT NAND GATE 8-INPUT NAND GATE VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD

circuit diagram of 32-1 multiplexer

Abstract: 4 input multiplexer low power TTL 74ls153 truth table NOT gate 74 SN74LSXXXD SN74LSXXXN 74LS153 74LS352 SN54LSXXXJ 74LS153 multiplexer truth table
Contextual Info: SN54/74LS352 DUAL 4-INPUT MULTIPLEXER The SN54 / 74LS352 is a very high-speed Dual 4-input Multiplexer with Common Select inputs and individual Enable inputs for each section. It can select two bits of data from four sources. The two buffered outputs present

74LS348

Abstract: G104 74LS848 LS348 SN54LSXXXJ SN74LSXXXN
Contextual Info: SN54/74LS348 SN54/74LS848 8-INPUT PRIORITY ENCODERS WITH 3-STATE OUTPUTS The SN54 / 74LS348 and the SN54 / 74LS848 are eight input priority encoders which provide the 8-line to 3-line function. The outputs A0 – A2 and inputs (0 – 7) are active low. The active low input

74L8138

Abstract: SC80C451 read/74L8138
Contextual Info: ’four Choice 87C51 OTP » » m m rn rn or Introducing W SI’s New P S D 211R Programmable Microcontroller Peripheral for Cost Sensitive Applications Replace all this. PLD/LOGIC 1 GV, Z O V 8 , Z 2 V 1 0 , etc. Your Low Cost MCU 80C31 G8HC11 74LS373 74L8138/PLD

Contextual Info: SN54LS395A, 74LS395A 4-BIT CASCADABLE SHIFT REGISTERS WITH 3 STATE OUTPUTS OCTO BER 1976 - RE V ISE D M A R C H 1988 Three-State, 4 Bit, Cascadable, ParalleMn, Parallel-Out Registers SN 54LS395A . . . J OR W PACKAGE SN 74LS395A . . . D OR N PACKAGE T O P V IE W

Contextual Info: GD54/74LS367A HEX BUS DRIVERS WITH 3-STATE OUTPUTS Feature • 3-State Outputs Drive Bus Line or Buffer Memory Address Registers • Choice of True or Inverting Outputs Pin Configuration Vcc G2 6A 6Y 5A 5Y 4A 4Y Description These hex buffers and line drivers are designed

ls378

Abstract: 74LS377 74LS174 74LS175 74LS378 74LS379
Contextual Info: SN54/74LS377 SN54/74LS378 SN54/74LS379 OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 / 74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a

D Flip Flops

Abstract: 74ls175 pin diagram 74ls376 4LS08 74LS175 LS08 AM2919 CD0017
Contextual Info: 80S~ISZUJV/Z0S~ISZU1V A m 25LS 07/A m 25LS08 Hex/Q uad Parallel D Registers with Register Enable DISTINCTIVE CHARACTERISTICS • • • • 4-bit and 6-bit parallel registers Com m on Clock and Common Enable Positive edge triggered D flip flops Second sourced by Tl as 54LS/74LS37B and 379

74ls347

Abstract: LS 347 LS 373 54LS347DM 54LS347FM 74LS347DC 74LS347FC 74LS347PC
Contextual Info: 347 C O N N E C T IO N D IA G R A M P IN O U T A 54LS/74LS347V q - 1- -1— BCD TO 7-SEGMENT DECODER/DRIVER Ao [ T 16] Vcc Ai T TilT l t î ï lâ |T BI/RBO [ I jU b R B l[? a2|T TT] c A3 [ T 7Ö1 d (T ~9~]e g n d L O G IC SYM BO L

TTL LS 7406

Abstract: el 7406 74l804 ls 7404 7404 ls 74114 ic 74132 IC 7404 IC TTL 7402 TTL IC 7405
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D7 54/7430, 54H/74H30 54S/74S30, 54LS/74LS30 Vcc NC r r r NC r D8 54S/74S133, 54LS/74LS133 Vcc NC r fi fi Ili ill HI Li Lil lil GND LzJ R R R R F IR R F I Vcc E RRRRRRRFl LiJ ikj Lil l±J UJ LsJ IzJ GND LU D11