74LVQ1 Search Results

74LVQ11

Abstract: 74LVQ11M 74LVQ11MTR 74LVQ11TTR TSSOP14
Contextual Info: 74LVQ11 TRIPLE 3-INPUT AND GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4.7ns TYP. at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING

74LVQ125

Abstract: 74LVQ125SC 74LVQ125SJ LVQ125 M14A M14D
Contextual Info: 74LVQ125 Low Voltage Quad Buffer with 3-STATE Outputs General Description Features The LVQ125 contains four independent non-inverting buffers with 3-STATE outputs. n Ideal for low power/low noise 3.3V applications n Guaranteed simultaneous switching noise level and

74LVQ158

Abstract: 74LVQ158M 74LVQ158MTR 74LVQ158TTR PO13H TSSOP16
Contextual Info: 74LVQ158 LOW VOLTAGE QUAD 2 CHANNEL MULTIPLEXER INV. • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.5 ns (TYP.) at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.2V (TYP.) at VCC = 3.3V

ds0113

Contextual Info: R C H II_ D E M IC O N D U C T O R t 74LVQ157 Low Voltage Quad 2-Input Multiplexer General Description Features The LVQ157 is a high-speed quad 2-input m ultiplexer. Four bits of data from tw o sources can be selected using the com ­ mon S elect and Enable inputs. The fo u r outputs present the

Contextual Info: 74LVQ138 3 TO 8 LINE DECODER INVERTING . HIGH SPEED: tPD = 5.5 ns (TYP.) at Vcc = 3.3V • COMPATIBLE WITH TTL OUTPUT . LOW POWER DISSIPATION: Ice = 4 |oA (MAX.) at T a = 25 °C . LOW NOISE: V olp = 0.2 V (TYP.) at V c c = 3 .3 V ■ 75Q TRANSMISSION LINE DRIVING

Contextual Info: SG S-TH O M SO N 74LVQ157 M0 gl3 l[LI(3ra [S!]D(BS LOW VOLTAGE QUAD 2 CHANNEL MULTIPLEXER . HIGHSPEED: tpD = 5 ns (TYP. at Vcc =3.3V . INPUT & OUTPUT TTL COMPATIBLE LEVELS . LOW POWER DISSIPATION: Ice = 4 |xA (MAX.) at TA = 25 °C . LOW NOISE: V o lp = 0.2V (TYP.) at V c c = 3.3V

Contextual Info: Æ T SGS-THOMSON D lsi S IILICTIs! iD©S 74LVQ125 QUAD BUS BUFFERS (3-STATE) . HIGH SPEED: tpD = 5 ns (TYP.) atVcc =3.3V . COMPATIBLEWITH TTL OUTPUTS . LOW POWER DISSIPATION: Ice = 4 |xA (MAX.) at T a = 25 °C . LOW NOISE: V olp = 0.3 V (TYP.) at V c c = 3.3V

74LVQ161

Abstract: 74LVQ161MTR 74LVQ161TTR TSSOP16
Contextual Info: 74LVQ161 SYNCHRONOUS PRESETTABLE 4-BIT COUNTER • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 180 MHz TYP. at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V

74LVQ10

Abstract: 74LVQ10MTR 74LVQ10TTR TSSOP14
Contextual Info: 74LVQ10 TRIPLE 3-INPUT NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.3ns TYP. at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING

74LVQ14

Abstract: 74LVQ04 74LVQ14MTR 74LVQ14TTR TSSOP14
Contextual Info: 74LVQ14 LOW VOLTAGE CMOS HEX SCHMITT INVERTER • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 6 ns TYP. at VCC = 3.3 V HYSTERESIS INPUT VOLTAGE: VH = 650mV (TYP.) at VCC = 3.0 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2µA(MAX.) at TA=25°C

d801

Abstract: 74LVQ157 74LVQ157SC 74LVQ157SJ LVQ157 M16A M16D
Contextual Info: E M IC D N D U C T O R t 74LVQ157 Low Voltage Quad 2-Input Multiplexer General Description Features The LVQ157 is a high-speed quad 2-input m ultiplexer. Four bits of data from tw o sources can be selected using the com ­ mon Select and Enable inputs. T he four outputs present the

P013H

Contextual Info: 74LVQ157 LOW VOLTAGE QUAD 2 CHANNEL MULTIPLEXER • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5 ns TYP. at VCC = 3.3V INPUT & OUTPUT TTL COMPATIBLE LEVELS LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.2V (TYP.) at VCC = 3.3V

74LVQ14

Abstract: 74LVQ04 74LVQ14MTR 74LVQ14TTR TSSOP14
Contextual Info: 74LVQ14 LOW VOLTAGE CMOS HEX SCHMITT INVERTER • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 6 ns TYP. at VCC = 3.3 V HYSTERESIS INPUT VOLTAGE: VH = 650mV (TYP.) at VCC = 3.0 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2µA(MAX.) at TA=25°C

74LVQ125

Contextual Info: October 1995 74LVQ125 Low Voltage Quad Buffer with TRI-STATE Outputs General Description Features The LVQ125 contains four independent non-inverting buff­ ers with TRI-STATE outputs. • Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and

74LVQ14

Abstract: 74LVQ14M 74LVQ14T TSSOP14
Contextual Info: 74LVQ14 HEX SCHMITT INVERTER • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 6 ns TYP. at VCC = 3.3V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING

74LVQ174

Abstract: 74LVQ174M 74LVQ174T LVQ174 TSSOP16
Contextual Info: 74LVQ174 HEX D-TYPE FLIP FLOP WITH CLEAR • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 150 MHz TYP. at VCC = 3.3V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V

74LVQ138

Abstract: 74LVQ138M 74LVQ138T LVQ138 TSSOP16
Contextual Info: 74LVQ138 3 TO 8 LINE DECODER INVERTING • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.5 ns (TYP.) at VCC = 3.3V COMPATIBLE WITH TTL OUTPUT LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.2 V (TYP.) at VCC = 3.3V

74LVQ174

Abstract: 74LVQ174SC 74LVQ174SJ LVQ174 M16A M16D
Contextual Info: Revised June 2001 74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset General Description Features The LVQ174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to

74LVQ125

Abstract: 74LVQ125SC 74LVQ125SJ LVQ125 M14A M14D
Contextual Info: Revised June 2001 74LVQ125 Low Voltage Quad Buffer with 3-STATE Outputs General Description Features The LVQ125 contains four independent non-inverting buffers with 3-STATE outputs. • Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and

74LVQ138

Abstract: 74LVQ138M 74LVQ138MTR 74LVQ138TTR PO13H TSSOP16
Contextual Info: 74LVQ138 3 TO 8 LINE DECODER INVERTING • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.5ns (TYP.) at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.2V (TYP.) at VCC = 3.3V

74LVQ163

Abstract: 74LVQ163M 74LVQ163MTR 74LVQ163TTR PO13H TSSOP16
Contextual Info: 74LVQ163 SYNCHRONOUS PRESETTABLE 4-BIT COUNTER • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 180 MHz TYP. at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V

74LVQ157

Abstract: 74LVQ157M 74LVQ157MTR 74LVQ157TTR PO13H TSSOP16
Contextual Info: 74LVQ157 LOW VOLTAGE QUAD 2 CHANNEL MULTIPLEXER • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 7 ns TYP. at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.2V (TYP.) at VCC = 3.3V

74LVQ174

Abstract: 74LVQ174SC 74LVQ174SCX 74LVQ174SJ 74LVQ174SJX LVQ174
Contextual Info: LVQ174 <ßN a t i o n a l Semiconductor 74LVQ174 Low Voltage Hex D Flip-Flop with Master Reset General Description Features The LVQ174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the O inputs is transferred to storage

Contextual Info: Æ T SG S-TH O M SO N D lsi S IILICTIs! iD©S 74LVQ174 HEX D-TYPE FLIP FLOP WITH CLEAR . HIGHSPEED: fM A X = 150 MHz (TYP.) at Vcc =3.3V . COMPATIBLE WITH TTL OUTPUTS . LOW POWER DISSIPATION: Ice = 4 |xA (MAX.) at TA = 25 °C . LOW NOISE: V olp = 0.3 V (TYP.) at Vcc = 3.3V