75451 TTL Search Results

Drivers

Abstract: TO-99 ttl nand gate ttl NAND gate circuit TO99 75473 75491
Contextual Info: FAIRCHILD INTERFACE AUXILIARY DRIVERS» Circuit Function Output Current mA Max Output Voltage-V Latchup Voltage V (Min) Drivers per Package Logic/Connection Diagram 55/75451 Dual D rivers TTL — AN D 300 30 20 30 2 117 TO-99 6T,9T 2 55/75452 Dual D rivers

dvr circuit diagram

Abstract: 74LS247 ttl 74141 TTL 74ls247 74LS248 74LS249 75431 8T13 8T14 8T24
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS INTERFACE 115 55/75325 116 55/75430, 55/75450, 55/75460 117 55/75431, 55/75451 55/75461, 55/75471 SOURCE 118 55/75432, 55/75452, 55/7562, 55/7572 121 8T13, 8T23, 55/75121, 75123 119 55/75433, 55/75453, 55/75463, 55/75473

75451ATC

Abstract: 75452ATC
Contextual Info: 55/75450A • 55/75451A • 55/75452A 55/75453A • 55/75454A DUAL PERIPHERAL DRIVERS FAIRCHILD LINEAR INTEGRATED C IRC U IT S GENERAL DESCRIPTION — The 55/75450A, 55/75451 A , 55/75452A, 55/75453A and 55/75454A are Dual High Speed General Purpose Interface

TTL 74LS244

Abstract: 74LS244 diagram 75431 74LS244 74LS240 74LS241 74S140 8T13 8T14 8T23
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS INTERFACE 115 55/75325 116 55/75430, 55/75450, 55/75460 117 55/75431, 55/75451 55/75461, 55/75471 SOURCE 118 55/75432, 55/75452, 55/7562, 55/7572 119 55/75433, 55/75453, 55/75463, 55/75473 121 I22 8T13, 8T23, 55/75121, 75123

TTL 7440

Abstract: 8T23 Fairchild 9614 i24l 8T13 8T14 8T24 uA1488 9637A ttl 111
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS INTERFACE 115 55/75325 116 55/75430, 55/75450, 55/75460 117 55/75431, 55/75451 55/75461, 55/75471 SOURCE 118 55/75432, 55/75452, 55/7562, 55/7572 121 8T13, 8T23, 55/75121, 75123 119 55/75433, 55/75453, 55/75463, 55/75473

4104B

Abstract: 75325 75431 75121 4049B 4050B 8T13 8T14 8T23 8T24
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS INTERFACE 115 55/75325 116 55/75430, 55/75450, 55/75460 117 55/75431, 55/75451 55/75461, 55/75471 SOURCE 118 55/75432, 55/75452, 55/7562, 55/7572 121 8T13, 8T23, 55/75121, 75123 119 55/75433, 55/75453, 55/75463, 55/75473

9T TRANSISTOR

Abstract: 75451 ttl NAND gate circuit TO-99 DTL Fairchild TO-100 8pin tic 122 75452 8T23 8T24
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS INTERFACE 115 55/75325 116 55/75430, 55/75450, 55/75460 117 55/75431, 55/75451 55/75461, 55/75471 SOURCE 118 55/75432, 55/75452, 55/7562, 55/7572 121 8T13, 8T23, 55/75121, 75123 119 55/75433, 55/75453, 55/75463, 55/75473

DTL Fairchild

Abstract: 75450 8T14 tic 122 8T13 8T23 8T24 SH2001 SH2002 SH2200
Contextual Info: FAIRCHILD LO G IC /C O N N EC TIO N DIAGRAMS INTERFACE 115 55/75325 116 55/75430, 55/75450, 55/75460 117 55/75431, 55/75451 55/75461, 55/75471 SOURCE 118 55/75432, 55/75452, 55/7562, 55/7572 121 8T13, 8T23, 55/75121, 75123 119 55/75433, 55/75453, 55/75463, 55/75473

3614

Contextual Info: DS3611/3612/3613/3614-N.T DESCRIPTION PIN CONFIGURATIONS T T h e DS3611 series o f dual p e riphe ral d rivers was designed fo r a p p lic a tio n s w here h ig h e r breakdow n volta ge is re q u ire d than th a t provided by th e 75451 series. P A C K A G E

g554

Contextual Info: 55/75450B-F.N • 55/75451 B /2 B /3 B /4 B -N .T DESCRIPTION FEATURES Series 55450B/75450B d ual pe riphe ral d riv ­ ers are a fa m ily o f versatile devices designed fo r use in system s th a t e m p lo y T T L o r DTL logic. The 55450B/75450B fa m ily is fu n c ­

Ferroxcube 3C8

Abstract: core 3c8 7405 power regulator in4934 NE5560 EC35 switching power ferroxcube core 3c8 Ferroxcube 3C8 4229 Ferroxcube core K3019PL_3C8
Contextual Info: INTEGRATED CIRCUITS AN122 NE5560 Push-pull regulator application 1988 Dec Philips Semiconductors Philips Semiconductors Application note NE5560 Push-pull regulator application INTRODUCTION NE/SE5560 Push-Pull Regulator This application describes the use of the

TO-99

Abstract: 75453 B1 9A TTL nand 8T13 8T14 8T23 8T24 TO99 75431
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS INTERFACE 115 55/75325 SOURCE 118 55/75432, 55/75452, 55/7562, 55/7572 116 55/75430, 55/75450, 55/75460 119 55/75433, 55/75453, 55/75463, 55/75473 121 I22 8T13, 8T23, 55/75121, 75123 8T14, 8T24, 55/75122, 75124 | Vcc I IN 8 6

74 TTL PACKAGE OUTLINES

Abstract: 75451ATC 1606B 55451A 75451ARC
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

DTL or TTL integrated logic circuits

Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 95 9 5 * Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

75451N

Abstract: 75452N 75451 TAG 8510 uj55 tranzystor UCY75452N 75452H
Contextual Info: U N IT R O UCY 75451N UCY 75452N C EM i Uklady UCT 75451N i UCY 75452 podwó jnyroi dwuwejàclowymi ukïadami poérednics^oymi /interface./ przeasnacsonymi do og<51nego süastosowania* ükiady s&adafc siç s: - dwóch bramek HAND /ukiad TOY 75451N/, - dwóch bramek AND /ukiad UGY 75452N/,

NE564

Abstract: 2N2366 NE564 equivalent ne554 series and parallel resonance 74HCT73 74HCT73 equivalent Quartz crystals General Introduction AN182 NE527
Contextual Info: INTEGRATED CIRCUITS AN182 Clock regenerator with crystal-controlled phase-locked loop VCO NE564 1991 Dec Philips Semiconductors Philips Semiconductors Application note Clock regenerator with crystal-controlled phase-locked loop VCO (NE564) AN182 “second-order” system. An RC series filter combination will cause a

75450APC

Abstract: 9109 DC fairchild ECL 75450a
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 . 0 0.4 90 440 TO-86 6A.9A 9 5 9 5 * Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver

DTL Fairchild

Abstract: SH2002 75450-DUAL 75453 75450 SH2001 SH2200 SH2201 SH3011 75451 ttl
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS HYBRID H2 SH2714 H1 SH0002 1 Vi+ R2 5 k INPUT O1 C NU LLA r V2+ -0 2 ri NU LL A 3 E3 INV. INPU T A -O 3 NO N-INV. INPUT A 8 0 - OUTPUT V -B -0 4 e4 O UTPUT B -0 6 Q2 V +B R1 5 k . Ò 7 v 2-O 6 V i - H4 SH1S49 13-12

75450

Abstract: SH2002 DTL Fairchild ttl transistor for nand SH1549 SH1552 SH2001 SH2200 SH2201 75454
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS HYBRID H6 SH3002 H7 SH3003 _ 10^ V+ _ ”i I I. vsw VSW I — 0 ° — i|: l-— — — GND O- o — 5 GND 5 -o 17 “ •O’" 6 V- H8 SH3011 Vcc 5 13 13-13 FAIRCHILD HYBRIDS INTERFACE Output Current A Max Output Standoff

a 4514 v

Abstract: 4514 PIN DIAGRAM
Contextual Info: PWR-DRV451-4 High-voltage Peripheral Drivers 200/300 V 200 mA per Channel_ POWER INTEGRATIONS, INC. Product Highlights Controls High-voltage Peripheral Devices • • • • • Relays and solenoids L am ps and gas-discharge displays M otors Interface to P-channel pow er M O SFETs

74LS247

Abstract: 75492 TTL 74ls247 ttl 74141 9T TRANSISTOR 74LS248 MA5558 D135 D141 D143
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS INTERFACE I26 75492, 9664 124 9613 [14 □ 13 □ 12 □ 11 □ 10 □ 9 □ 8 □ 8 OUTPUT A □ Vcc □ OUT B 7 2 +IN A Q 3 -IN A ^ 4 GND 6 □ +IN B 5 □ -IN B 2 OUT D Vss OUT C OUT C IN C I27 I28 mA5SS 131 7528, 7529

75450apc

Abstract: 10125 ecl to ttl fairchild 9112 7S45 pin diagram for all 74 series ttl gates
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 . 0 0.4 90 440 TO-86 6A.9A 9 5 9 5 * Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver

ttl transistor for nand

Abstract: 75450 SH2201 DTL Fairchild SH2001 SH1549 SH1552 SH2002 SH2200 SH3002
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS HYBRID H1 H2 S H 0002 S H 2714 1 Vi+ R2 5 k INPUT O1 NU LL A V2+ -0 2 ri NU LLA C r 3 E3 INV. INPU T A -O 3 4 NO N-INV. INPUT A 8 0 - OUTPUT 5 V -B -0 4 6 e4 O UTPUT B -0 6 Q2 V +B R1 5 k . Ò 7 C L C C C v 2-O 6 V i-