Untitled
Abstract: No abstract text available
Text: Customer Information Sheet DRAWING No.; M 80-887XXXX SH EET 2 OF 2 | IF IN DOUBT - ASK | ç | NOT TO S C A L E 1 SPECIFICATIONS; 2.00 x No, OF WAYS PER ROW + 3.15 MAX cs <s r\i (3.0)- A L L DIMENSIONS IN mm THIRD ANGLE PROJECTION - d ’ZZZZZBr -e 7777m-
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80-887XXXX
7777m-
M80-887XXXX
B5741-2XX-F-T-X
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Untitled
Abstract: No abstract text available
Text: HIIICRTRLYST Umili S E M I C O N D U C T O R CAT64LC10/20/40 1K/2K/4K-Bit Serial E2PROM FEATURES • SPI Bus Compatible Commercial and Industrial Temperature Ranges ■ Low Power CMOS Technology Power-Up Inadvertant W rite Protection ■ 2.5V to 6.0V Operation
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CAT64LC10/20/40
CAT64LC10/20/40
64LC10SI-2
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424260 NEC
Abstract: 424260-80
Text: DATA SHEET NEC MOS INTEGRATED CIRCUIT /¿PD42S4260, 424260 4 M-BIT DYNAMIC RAM 256 K-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE Description T h e //P D 42S 4260,424260 are 262,144 w o rd s by 16 b its d y n a m ic C M OS R A M s. T h e fa s t page m o d e and b yte
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PD42S4260,
16-BIT,
/iPD42S4260
44-pin
40-pin
0057Li51
424260 NEC
424260-80
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j477
Abstract: V54C365164VC
Text: M O S E L V IT E L IC V54C365164VC HIGH PERFORMANCE 143/133/125 MHz 3.3 V 0 L T 4 M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16 PRELIMINARY 7 75 8PC 8 System Frequency fCK 143 MHz 133 MHz 125 MHz 125 MHz Clock Cycle Tim e (tcK 3) 7 ns 7.5 ns 8 ns 8 ns Clock Access Tim e (tAC3) CAS Latency = 3
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V54C365164VC
V54C365164VC
54-Pin
L0-40
j477
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sl 5066
Abstract: SKHI 10 op CAT64LC20 5066e
Text: böE D ntEL^S Q Q G 1 7 4 S D7b CST CATALYST SEMICONDUCTOR Advance in llC R T R L Y S T • f i l i S E M I C O N D U C T O R CAT64LC20/CAT64LC20I 2K-Bit SERIAL E2PROM FEATURES ■ Power-Up Inadvertant W rite Protection ■ SPI Bus Compatible ■ Low Power CMOS Technology
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qqg174s
CAT64LC20/CAT64LC20I
CAT64LC20Z)
CAT64LC20
CAT64LC20I
CAT64LC20/CAT64LC20I
sl 5066
SKHI 10 op
5066e
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SKHI 65
Abstract: CAT64LC40 SKHI 10 op
Text: bûE nt.Hb'ìS □0D17SM DäT » Advance CST CATALYST S EM ICO NDUC TOR S E M I C O N D U C T O R CAT64LC40/CAT64LC40I 4K-Bit SERIAL E2PROM FEATURES • SP I Bus C o m p atib le P o w er-U p In a d v e rtan t W rite P rotectio n ■ L o w P o w e r C M O S T e c h n o lo g y
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CAT64LC40/CAT64LC40I
CAT64LC40Z)
CAT64LC40
CAT64LC40I
CAT64LC40/CAT64LC40I
SKHI 65
SKHI 10 op
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82385
Abstract: intel 80386 block diagram pin configuration of intel 80386 80386 AW12 cache memory OF intel 80386 intel 80386 pin diagram INTEL 80386 25 TA11 chip intel 82385
Text: VITEUC V63C330 HIGH PERFORMANCE, LOW POWER 8K x 16 B IT CACHE CMOS STATIC RAM Features Description • Designed for 32KB, 64KB and 128KB Cache Implementation ■ Directly interfaces with 82385 Cache Controller High speed • Designed for 80386 Systems at 33/25/20
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V63C330
128KB
aw12-
82385
intel 80386 block diagram
pin configuration of intel 80386
80386
AW12
cache memory OF intel 80386
intel 80386 pin diagram
INTEL 80386 25
TA11 chip
intel 82385
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Untitled
Abstract: No abstract text available
Text: M O SEL VITELIC V53C516405A 4M X 4 EDO PAGE MODE CMOS DYNAMIC RAM V53C516405A 50 60 Max. RAS Access Time, tpj^c 50 ns 60 ns Max. Column Address Access Time, (tcAA) 25 ns 30 ns Min. Extended Data Out Page Mode Cycle Time, (tpc) 20 ns 25 ns Min. Read/Write Cycle Time, (tpc)
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V53C516405A
cycles/64
24/26-pin
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Untitled
Abstract: No abstract text available
Text: MOSEL VITELIC V53C316405A 3.3 VOLT 4M x 4 EDO PAGE MODE CMOS DYNAMIC RAM V53C316405A 50 60 Max. RAS Access Time, tRAC 50 ns 60 ns Max. Column Address Access Time, (tcAA) 25 ns 30 ns Min. Extended Data Out Page Mode Cycle Time, (tpc) 20 ns 25 ns Min. Read/Write Cycle Time, (tRc)
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V53C316405A
cycles/64
24/26-pin
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Untitled
Abstract: No abstract text available
Text: M O S E L V IT E L IC V53C316405A 3.3 VOLT 4M x 4 EDO PAGE MODE CMOS DYNAMIC RAM V53C316405A 50 60 Max. RAS Access Time, tRAC 50 ns 60 ns Max. Column Address Access Time, (tcAA) 25 ns 30 ns Min. Extended Data Out Page Mode Cycle Time, (tpc) 20 ns 25 ns Min. Read/Write Cycle Time, (tpc)
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V53C316405A
cycles/64
24/26-pin
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Untitled
Abstract: No abstract text available
Text: M O S E L V IT E L IC V100J9 and V100J8 1M X 9, 1M X 8 BIT FAST PAGE MODE CMOS DYNAMIC RAM MEMORY MODULE 60/60L 70/70L 80/80L Max. RAS Access Time, tRAf0 HIGH PERFORMANCE V100J8/9 60 ns 70 ns 80 ns Max. Column Address Access Time, (trA A 30 ns 35 ns 40 ns
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V100J9
V100J8
60/60L
70/70L
80/80L
V100J8/9
V100J8/9L
V100S
xzzzzzzzz7777777
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rca thyristor manual
Abstract: HN623258 101490
Text: Quick Reference Guide to Hitachi 1C Memories Package Information Reliability of Hitachi 1C Memories Applications MOS Static RAM MOS Pseudo Static RAM Application Specific Memory MOS Dynamic RAM MOS Dynamic RAM Module MOS Mask ROM MOS PROM ECL RAM P> Jc^< j
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ic 7485
Abstract: pin diagram for IC 7485 pin diagram for IC 7485 input id pin diagram ic 7485 7485 aa ci 7485
Text: PRELIMINARY CYPRESS SEMICONDUCTOR CYM7485 128K Write-Through Secondary Cache Module Features Functional Description • 128-Kbyte direct-mapped, writethrough, zero-wait-state secondary cache module • Operates with 33-MHz Intel 486 pro cessors • Uses low-cost CMOS asynchronous
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128-Kbyte
33-MHz
64-position
CYM7485
7485Z
--33C
128-Pin
-00058--A
ic 7485
pin diagram for IC 7485
pin diagram for IC 7485 input id
pin diagram ic 7485
7485 aa
ci 7485
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IGNITOR Z 400 M
Abstract: 67551 Thyratron Ignitron PL6755 Scans-00180016 thyratron tube rs tube scans-0018001 redresseur
Text: PHILIPS PL 6755 THYRATRON, mercury-vapour and inert gas-rilled, triode THYRATRON, triode à vapeur de mercure et à gaz rare STROMTORRÖHRE, Triode mit Quecksilberdampf- und Edelga? füllung Application: A. Dimming Installations for stage-lighting, fluorescent lighting etc.
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PL6755
IGNITOR Z 400 M
67551
Thyratron
Ignitron
PL6755
Scans-00180016
thyratron tube
rs tube
scans-0018001
redresseur
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Untitled
Abstract: No abstract text available
Text: DATA SHEET MOS INTEGRATED CIRCUIT / iP D 42S 17405L , 4217405L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 4 M-WORD BY 4-BIT, EDO Description The ¿¡PD42S17405L, 4217405L are 4,194,304 words by 4 bits CMOS dynamic RAMs with optional EDO. EDO is a kind of the page mode and is useful for the read operation.
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17405L
4217405L
PD42S17405L,
4217405L
PD42S17405L
26-pin
VP15-207-3
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TC5564AFL-15TOSHIBA
Abstract: TC5564AFL-15 TC5564APL15
Text: TOSHIBA MOS MEMORY PRODUCTS 8 ,192 WORD X T C 5564 A P L-1 5,T C 5 56 4A P L -2 0 T C 5 5 6 4 A F L -1 5 ,T C 5 5 6 4 A F L -2 0 8 BIT CMOS STATIC RAM PRELIMINARY DESCRIPTION TC 5564APL is 6 5 5 3 6 bits static random access m em ory organized as 8 1 9 2 w ords by 8 bits using
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5564APL
TC5564AFL-20
F28GA-P)
TC5564AFL-15TOSHIBA
TC5564AFL-15
TC5564APL15
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NN5118160A
Abstract: NN5118160B WA137
Text: NN5118160A / NN5118160B series Fast Page Mode CMOS 1Mx 16bit Dynamic RAM NPN a DESCRIPTION The NN5118160A / NN5118160B series is a high performance CMOS Dynamic Random Access Memory organized as 1,048,576 words by 16 bits. The NN5118160A / B series is fabricated with advanced CMOS technology and designed with
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NN5118160A
NN5118160B
16bit
NN5118160A/NNS118160B
WA137
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d482444
Abstract: No abstract text available
Text: DATA SHEET NEC / MOS INTEGRATED CIRCUIT / juPD482444, 482445 4M-Bit Dual Port Graphics Buffer 256K-WORD BY 16-BIT Description The ¿¿PD482444 and ¿¿PD482445 have a random access port and a serial access port. The random access port has a 4M -bit 262, 144 words x 16 bits m em ory cell array structure. The serial access port can perform clock
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uPD482444
uPD482445
256K-WORD
16-BIT
PD482444
PD482445
d482444
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HM53462P
Abstract: No abstract text available
Text: HM53462 Series 65,536-Word x 4-Bit Multiport CMOS Video RAM with Logic Operation Mode • DESCRIPTION The HM53462 is a 262,144-bit multiport memory equipped with a 64k-word x 4-bit Dynamic RAM port and a 256-word x 4-bit Serial Access Memory (SAM) port.
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HM53462
536-Word
144-bit
64k-word
256-word
024-bit
HM53462P
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Untitled
Abstract: No abstract text available
Text: M O S E L V IT E L IC PRELIMINARY V53C516400A 4M x 4 FAST PAGE MODE CMOS DYNAMIC RAM V53C516400A 50 60 Max. RAS Access Tim e, tRAC 50 ns 60 ns Max. Column Address Access Time, (tcAA) 25 ns 30 ns Min. Page Mode Cycle Time, (tpc) 35 ns 40 ns Min. Read/W rite Cycle Time, (tpc)
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V53C516400A
cycles/64
24/26-pin
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414256-10
Abstract: 414256 MSM414256-10 MSM414256-12 MSM414256-12RS
Text: O K I S E M I C O N D U C T O R GR O U P ôi OKI » Ë J b 7 E M S M 0 OODSSbt, 5 | ~ ¿.6724240 O K I S E M I C O N D U C T O R G R O U P semiconductor 89D 02566 MSM414256RS 262,144-WORD X ~J7 D 4-BIT DYNAMIC RAM GENERAL DESCRIPTION The MSM414256RS is a new generation dynamic RAM organized as 262,144 words by 4 bits.
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b72ME40
MSM414256RS
144-WORD
MSM414256RS
20-pin
414256-10
414256
MSM414256-10
MSM414256-12
MSM414256-12RS
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chn 619
Abstract: LSI SF 2300
Text: O K I Semiconductor MSM6588 MSM6588 contents GENGERAL DESCRIPTION. 568 FEATURES. 568
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MSM6588
MSM6388
MSM6588
096MHz
chn 619
LSI SF 2300
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Untitled
Abstract: No abstract text available
Text: M O S E L V ÏÏT E U C V53C664A 6 4 K x 16 BIT FAST PAGE MODE BYTE WRITE CMOS DYNAMIC RAM 60/60L 70/70L 80/S0L Max. RAS Access Time, tR A r 60 ns 70 ns 80 ns Max. Column Address Access Time, (tr 4 i ) 35 ns 40 ns 45 ns Min. Fasi Page Mode Cycle Time, (tp r )
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V53C664A
60/60L
70/70L
80/S0L
VS3C664A
V53C664AL
200nA
16-bit
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Untitled
Abstract: No abstract text available
Text: M O SEL V IT E L IC V52C8256 MULTIPORT VIDEO RAM WITH 256K X 8 DRAM AND 512 X 8 SAM HIGH PERFORMANCE V52C8256 PRELIMINARY 60 70 80 Max. RAS Access Time, I raq 60 ns 70 ns 80 ns Max. CAS Access Time, (tCAC) 15 ns 20 ns 25 ns Max. Column Address Access Time, (lM )
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V52C8256
V52C8256
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