79RCXX Search Results

RC32300

Abstract: RC32355 79RC32355 CRC-10 CRC-32
Contextual Info: 79RC32355 IDTTM InterpriseTM Integrated Communications Processor Features List SDRAM Controller – 2 memory banks, non-interleaved, 512 MB total – 32-bit wide data path – Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips – SODIMM support – Stays on page between transfers

C3243

Abstract: ATI Rage ITT K12 series switch IDT74FCT245 MIPS32 RC32 RC32434
Contextual Info: IDT T M InterpriseT M Integrated Communications Processor Device Overview PCI Interface – 32-bit PCI revision 2.2 complia nt – Supports host or satellite operation in both master and target modes – Support for synchronous and asynchronous operation – PCI clock supports frequencies from 16 MHz to 66 MHz

79RC32332

Abstract: FCT245 RC32300 RC32332 RC32364 RC5000
Contextual Info: RISCoreTM 32300 Family Integrated Processor Features 79RC32332—Rev. Y Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 512MB total SDRAM memory supported

RC32364

Abstract: RC5000 79RC32333 FCT245 RC32300
Contextual Info: 79RC32333 IDTTM InterpriseTM Integrated Communications Processor Features Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 512MB total SDRAM memory supported

IDT74FCT245

Abstract: MIPS32 RC32434
Contextual Info: RC32434 IDTTM InterpriseTM Integrated Communications Processor Device Overview PCI Interface – 32-bit PCI revision 2.2 compliant – Supports host or satellite operation in both master and target modes – Support for synchronous and asynchronous operation

CPU STI 7111

Abstract: 79RC32351 CRC-10 CRC-32 RC32300 RC32351
Contextual Info: 79RC32351 Integrated Communications Processor Features List SDRAM Controller – 2 memory banks, non-interleaved, 512 MB total – 32-bit wide data path – Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips – SODIMM support – Stays on page between transfers

RC32300

Abstract: 79RC32332 FCT245 RC32332 RC32364 RC5000
Contextual Info: RISCoreTM 32300 Family Integrated Processor Features 79RC32332 Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 256MB total SDRAM memory supported

AES-128

Abstract: IDT74FCT245 MIPS32 RC32300 RC32365 "ESP"
Contextual Info: RC32365 IDTTM InterpriseTM Integrated Communications Processor Device Overview – – – – – – – 2-way set associative LRU replacement algorithm 4 word line size Sub-block ordering Byte parity Per line cache locking Can be programmed on a page basis to implement writethrough no write allocate, write-through write allocate, or

HMS M11

Abstract: ITT K12 series switch AES-128 IDT74FCT245 MIPS32 RC32 RC323 RC32300 RC32365 d13 -620 gh
Contextual Info: IDT T M InterpriseT M Integrated Communications Processor Device Overview – – – – – – – 2-way set associa tive LRU replacement algorithm 4 word lin e size Sub-block ordering Byte parity Per line cache lockin g Can be programmed on a page basis to implement writethrough no write allocate, write-through write allocate, or

Contextual Info: RISCoreTM32300 Family Integrated Processor Features 79RC32334—Rev. Y Preliminary Information* Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 512MB total SDRAM memory supported

79RC32332

Abstract: FCT245 RC32300 RC32332 RC32364 RC5000
Contextual Info: 79RC32332—Rev. Y IDTTM InterpriseTM Integrated Communications Processor Features Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 512MB total SDRAM memory supported

Contextual Info: RC32365 IDTTM InterpriseTM Integrated Communications Processor Device Overview – – – – – – – 2-way set associative LRU replacement algorithm 4 word line size Sub-block ordering Byte parity Per line cache locking Can be programmed on a page basis to implement writethrough no write allocate, write-through write allocate, or

Contextual Info: RISCoreTM 32300 Family Integrated Processor Features 79RC32332 Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 256MB total SDRAM memory supported

Contextual Info: 79RC32355 Integrated Communications Processor Features List SDRAM Controller – 2 memory banks, non-interleaved, 512 MB total – 32-bit wide data path – Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips – SODIMM support – Stays on page between transfers

79RC32355

Abstract: CRC-10 CRC-32 RC32 RC323 RC32300 RC32355 Philips PE 1203
Contextual Info: IDT T M InterpriseT M Integrated Communications Processor Features List 79RC32355 SDRAM Controller – 2 memory banks, non-interleaved, 512 MB total – 32-bit wid e data path – Supports 4-bit, 8-bit, and 16-bit wid e SDRAM chips – SODIMM support – Stays on page between transfers

Contextual Info: RC32336 IDTTM InterpriseTM Integrated Communications Processor Device Overview The RC32336 device is a member of the IDT Interprise™ family of integrated communications processors. It provides an effective solution for small office/home office SOHO applications including gateways and

79RC32T355

Contextual Info: 79RC32355 IDTTM InterpriseTM Integrated Communications Processor Features List SDRAM Controller – 2 memory banks, non-interleaved, 512 MB total – 32-bit wide data path – Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips – SODIMM support – Stays on page between transfers

Contextual Info: 79RC32351 IDTTM InterpriseTM Integrated Communications Processor Features List SDRAM Controller – 2 memory banks, non-interleaved, 512 MB total – 32-bit wide data path – Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips – SODIMM support – Stays on page between transfers

Contextual Info: RC32434 IDTTM InterpriseTM Integrated Communications Processor Device Overview PCI Interface – 32-bit PCI revision 2.2 compliant – Supports host or satellite operation in both master and target modes – Support for synchronous and asynchronous operation

CPU STI 7111

Abstract: RC32300 STi 7111 79RC32T355
Contextual Info: 79RC32355 Integrated Communications Processor Features List SDRAM Controller – 2 memory banks, non-interleaved, 512 MB total – 32-bit wide data path – Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips – SODIMM support – Stays on page between transfers

Contextual Info: RISCoreTM32300 Family Integrated Processor Features 79RC32334—Rev. Y Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 512MB total SDRAM memory supported

79RC32332

Abstract: FCT245 RC32300 RC32332 RC32364 RC5000 EJTAG 1.53
Contextual Info: RISCoreTM 32300 Family Integrated Processor Features 79RC32332 Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 256MB total SDRAM memory supported

79RC32334

Abstract: FCT245 MIPS32 RC32300 RC32364 RC5000
Contextual Info: 79RC32334—Rev. Y IDTTM InterpriseTM Integrated Communications Processor Features Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 512MB total SDRAM memory supported

Contextual Info: 79RC32438 IDTTM InterpriseTM Integrated Communications Processor ◆ Memory and Peripheral Device Controller – Provides “glueless” interface to standard SRAM, Flash, ROM, dual-port memory, and peripheral devices – Demultiplexed address and data buses: 16-bit data bus, 26-bit