800MSPS Search Results

MAX2108

Abstract: TP2041 MAX105 MAX105ECS MAX107 TAD100
Contextual Info: 19-2006; Rev 0; 5/01 Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier In addition, the MAX105 provides LVDS digital outputs with an internal 6:12 demultiplexer that reduces the output data rate to one-half the sample clock rate. Data is output in two’s complement format. The MAX105 operates from a +5V analog supply and the LVDS output

Contextual Info: ADS5402 www.ti.com SLAS936A – MARCH 2013 – REVISED AUGUST 2013 Dual 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5402 FEATURES 1 • • • • • • • • • Dual Channel 12-Bit Resolution Maximum Clock Rate: 800 Msps Low Swing Fullscale Input: 1.0 Vpp

L5A1

Contextual Info: ADS5401 www.ti.com SLAS946 – APRIL 2013 Single 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5401 FEATURES 1 • • • • • • • • • Single Channel 12-Bit Resolution Maximum Clock Rate: 800 Msps Low Swing Fullscale Input: 1.0 Vpp

Contextual Info: ADS5402 www.ti.com SLAS936 – MARCH 2013 Dual 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5402 FEATURES 1 • • • • • • • • • Dual Channel 12-Bit Resolution Maximum Clock Rate: 800 Msps Low Swing Fullscale Input: 1.0 Vpp

Contextual Info: 19-2006; Rev 0; 5/01 Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier In addition, the MAX105 provides LVDS digital outputs with an internal 6:12 demultiplexer that reduces the output data rate to one-half the sample clock rate. Data is output in two’s complement format. The MAX105 operates from a +5V analog supply and the LVDS output

12x12mm BGA package thermal resistance

Abstract: DA5N
Contextual Info: ADS5402 www.ti.com SLAS939 – JANUARY 2013 Dual 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5402 FEATURES 1 • Dual Channel 12-Bit Resolution Maximum Clock Rate: 800 Msps Low Swing Fullscale Input: 1.0 Vpp Analog Input Buffer with High Impedance Input

12x12mm BGA package thermal resistance

Contextual Info: ADS5402 www.ti.com SLAS936 – MARCH 2013 Dual 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5402 FEATURES 1 • • • • • • • • • Dual Channel 12-Bit Resolution Maximum Clock Rate: 800 Msps Low Swing Fullscale Input: 1.0 Vpp

MAX105

Abstract: MAX105ECS MAX107 MAX2108 Electrical signal Splitter 10g TAD100 differential encoding in qam 10dBm
Contextual Info: 19-2006; Rev 0; 5/01 Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier In addition, the MAX105 provides LVDS digital outputs with an internal 6:12 demultiplexer that reduces the output data rate to one-half the sample clock rate. Data is output in two’s complement format. The MAX105 operates from a +5V analog supply and the LVDS output

Contextual Info: ADS5402 www.ti.com SLAS936B – MARCH 2013 – REVISED JANUARY 2014 Dual 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5402 FEATURES DESCRIPTION • • • • • • • • The ADS5402 is a high linearity dual channel 12-bit, 800 Msps analog-to-digital converter ADC easing

Electrical signal Splitter 10g

Contextual Info: 19-2006; Rev 0; 5/01 Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier In addition, the MAX105 provides LVDS digital outputs with an internal 6:12 demultiplexer that reduces the output data rate to one-half the sample clock rate. Data is output in two’s complement format. The MAX105 operates from a +5V analog supply and the LVDS output

Contextual Info: ADS5401 www.ti.com SLAS946A – APRIL 2013 – REVISED JANUARY 2014 Single 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5401 FEATURES DESCRIPTION • • • • • • • • The ADS5401 is a high linearity single channel 12-bit, 800 Msps analog-to-digital converter ADC easing

Contextual Info: ADS5401 www.ti.com SLAS946 – APRIL 2013 Single 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5401 FEATURES 1 • • • • • • • • • Single Channel 12-Bit Resolution Maximum Clock Rate: 800 Msps Low Swing Fullscale Input: 1.0 Vpp

Contextual Info: ADS5401 www.ti.com SLAS946 – APRIL 2013 Single 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5401 FEATURES 1 • • • • • • • • • Single Channel 12-Bit Resolution Maximum Clock Rate: 800 Msps Low Swing Fullscale Input: 1.0 Vpp

Contextual Info: ADS5401 www.ti.com SLAS946A – APRIL 2013 – REVISED JANUARY 2014 Single 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5401 FEATURES DESCRIPTION • • • • • • • • The ADS5401 is a high linearity single channel 12-bit, 800 Msps analog-to-digital converter ADC easing

GC5325

Abstract: TI6727
Contextual Info: GC5328 www.ti.com SLWS218A – OCTOBER 2009 – REVISED OCTOBER 2009 GC5328 Low-Power Wideband Digital Predistortion Transmit Processor Check for Samples: GC5328 FEATURES 1 • • • • • • • • Integrated DUC, CFR, and DPD Solution 20-MHz Max. Signal Bandwidth, Based on Max.

lm317

Abstract: 14CLK 500MSPS ADC08D500 AN-450
Contextual Info: ご注意：この日本語データシートは参考資料として提供しており内容が最新でない 場合があります。製品のご検討およびご採用に際しては、必ず最新の英文デー タシートをご確認ください。

Contextual Info: Sample & Buy Product Folder Support & Community Tools & Software Technical Documents DAC3283 SLAS693C – MARCH 2010 – REVISED MARCH 2015 DAC3283 Dual-Channel, 16-Bit, 800 MSPS, Digital-to-Analog Converter DAC 1 Features 3 Description • • The DAC3283 is a dual-channel 16-bit 800 MSPS

GC5325

Contextual Info: GC5328 www.ti.com SLWS218A – OCTOBER 2009 – REVISED OCTOBER 2009 GC5328 Low-Power Wideband Digital Predistortion Transmit Processor Check for Samples: GC5328 FEATURES 1 • • • • • • • • Integrated DUC, CFR, and DPD Solution 20-MHz Max. Signal Bandwidth, Based on Max.

SDR FPGA adc

Abstract: TXB17 lte20 free TMS320C6748 adaptive algorithm dpd GC533x DPD Application Note
Contextual Info: GC5330 GC5337 Preliminary www.ti.com SLWS226 A – DECEMBER 2010 – REVISED DECEMBER 2010 Wideband Transmit-Receive Digital Signal Processors Check for Samples: GC5330, GC5337 (Preliminary) FEATURES APPLICATIONS • • • • • • • • 1 • •

LTE MIMO repeater

Abstract: SDR FPGA adc rxa12 adaptive algorithm dpd
Contextual Info: GC5330 GC5337 SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011 www.ti.com Wideband Transmit-Receive Digital Signal Processors Check for Samples: GC5330, GC5337 FEATURES APPLICATIONS • • • • • • • • 1 • • • • • • • • •

Contextual Info: DAC3283 www.ti.com SLAS693A – MARCH 2010 – REVISED APRIL 2010 Dual-Channel, 16-Bit, 800 MSPS, Digital-to-Analog Converter DAC Check for Samples: DAC3283 FEATURES APPLICATIONS • • • • • • 1 • • • • • • • • • • • Dual, 16-Bit, 800 MSPS DACs

12x12mm BGA package thermal resistance

Abstract: fpga radar Analog Filter design
Contextual Info: ADS5404 www.ti.com SLAS945 – APRIL 2013 Dual Channel 12-Bit 500Msps Analog-to-Digital Converter Check for Samples: ADS5404 FEATURES 1 • • • • • • • • • • • Dual Channel 12-Bit Resolution Maximum Clock Rate: 500 Msps Low Swing Fullscale Input: 1.0 Vpp

IEEE-1596

Abstract: E5430 R161 022 BAV99ZXCT LC1210 AD9734 AD9735 AD9736 AVDD33 esd p3
Contextual Info: 10-/12-/14-Bit, 1200 MSPS DACS AD9734/AD9735/AD9736 FEATURES FUNCTIONAL BLOCK DIAGRAM RESET A reduced-specification LVDS interface is utilized to achieve the high sample rate. The output current can be programmed over a range of 8.66 mA to 31.66 mA. The AD973x family is

verilog code to generate sine wave

Abstract: open LVDS deserialization IP verilog code for sine wave using FPGA 0x0000011 C71B MB86064 fujitsu lvds standard BF15 D132 LVDS17
Contextual Info: High-Speed Data Interface for Stratix Devices & Fujitsu MB86064 DACs Application Note AN-316-1.0 Introduction Implementing the digital interface to drive a high-speed digital-toanalogue converter DAC is challenging. The conversion rates of highspeed DACs has increased significantly in recent years, so special design