80960MC Search Results

D15105

Abstract: 44fl5 271060 754for
Contextual Info: in te i 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS1 Sustained Execution at 25 MHz On-Chip Memory Management Unit

80960MC

Abstract: Dynamic Memory Refresh Controller M8259A
Contextual Info: 80960MC System Architecture 2 CHAPTER 2 80960MC SYSTEM ARCHITECTURE This chapter illustrates the flexibility and power o f the 80960M C system architecture using the advanced 32-bit 80960M C processor. It exam ines system configurations from a general perspective

80960MC

Contextual Info: Process Management 13 CHAPTER 13 PROCESS MANAGEMENT This chapter introduces the 80960MC processor’s process-management facilities. Included is a discussion of process-management concepts, the process-control block PCB , and the require­ ments for managing a single process. Chapter 14 describes the management of multiple

80960MC

Contextual Info: Instruction Reference 17 CHAPTER 17 INSTRUCTION REFERENCE This chapter provides detailed information about each of the instructions for the 80960MC processor. To provide quick access to information on a particular instruction, the instructions are listed alphabetically by assembly-language mnemonic. An explanation of the format and

Speed PI Controller

Abstract: AP 138B 114H 80960MC M82965
Contextual Info: AP-Bus Interface Using the BXU CHAPTER 8 AP-BUS INTERFACE USING THE BXU The M82965 Bus Extension Unit BXU is the key component in building multiprocessor designs with the 80960MC processor family. The BXUs connect to each other in an expandable matrix that

a4490

Abstract: 80960MC A80960MC25 i960 mc errata 80960KA 80960KB M8259A intel packaging handbook 240800
Contextual Info: 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Commercial • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ On-Chip Floating Point Unit

80960MC

Abstract: multi-processor
Contextual Info: 80960MC Multiprocessor System Architecture Q CHAPTER 6 80960MC MULTIPROCESSOR SYSTEM ARCHITECTURE This chapter illustrates the flexibility of the 80960MC system architecture using the advanced 32bit 80960MC processor and the 82965 Bus Extension Unit BXU in a multiprocessor design.

80960MC

Abstract: processor cross reference INTEL 80960 pipeline architecture
Contextual Info: Introduction to the 80960MC Microprocessor CHAPTER 1 INTRODUCTION TO THE 80960MC MICROPROCESSOR The 80960MC is the military version of the 80960 family, designed especially for high reliability embedded applications. At an operating frequency of 20 MHz, this high performance processor can

80960MC

Abstract: 8B16 8C16 8D16
Contextual Info: Interagent Communication 1y CHAPTER 11 INTERAGENT COMMUNICATION This chapter describes the interagent communication IAC mechanism for the 80960MC processor. Included is a description of the IAC-message structure, the intemal-IAC-message sending and receiving mechanism, and reference information on the available IAC messages.

80960MC

Contextual Info: Procedure Calls 4 CHAPTER 4 PROCEDURE CALLS This chapter describes the 80960MC processor’s procedure call and stack mechanism. It also describes the user-supervisor protection model, which provides protection for privileged procedures such as operating-system procedures.

processor

Abstract: 80960MC M82965
Contextual Info: Processor Management and Initialization g CHAPTER 9 PROCESSOR MANAGEMENT AND INITIALIZATION This chapter describes the facilities for initializing and managing the operation of the 80960MC processor. Included is an overview of the processor-management facilities and a

M82965

Contextual Info: 80960MC PRODUCT OVERVIEW This chapter provides an overview o f the architecture o f the 80960M C processor. The 80960M C processor is the m ilitary-grade m em ber o f a new fam ily o f processors from Intel. This processor family is based on a new 32-bit architecture called the 80960 architecture. The

230843

Abstract: intel intellec prompt 48 210997 80960 Programmer Reference manual 210918 mohawk 80960MC A-20
Contextual Info: 80960MC Programmer’s Reference Manual 1988 Order Number: 271081-001 inter LITERATURE To order Intel literature write or call: Intel Literature Sales Toll Free Number: P.O. Box 58130 800 548-4725* Santa Clara, CA 95052-8130 Use the order blank on the facing page or call our Toll Free Number listed above to order literature.

80960MC

Contextual Info: Debugging 16 CHAPTER 16 DEBUGGING This chapter describes the tracing facilities of the 80960MC processor, which allow the monitoring of instruction execution. OVERVIEW OF THE TRACE-CONTROL FACILITIES The 80960MC processor provides facilities for monitoring the activity o f the processor by

Contextual Info: ÄEW M i DNHF@IRßM!rilON in y 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at

80960MC

Abstract: INTEL 80960 pipeline architecture M82965 80960
Contextual Info: Introduction to the 80960 Architecture 2 CHAPTER 2 INTRODUCTION TO THE 80960 ARCHITECTURE This chapter provides an overview of the architecture on which the 80960MC processor is based. A NEW 32-BIT ARCHITECTURE FROM INTEL The 80960MC processor is the military-grade member of a new family of processors from

80960MC

Abstract: M8259A
Contextual Info: Interrupts 10 CHAPTER 10 INTERRUPTS This chapter describes the 80960MC processor’s interrupt handling facilities. It also describes how interrupts are signaled. OVERVIEW OF THE INTERRUPT FACILITIES An interrupt is a temporary break in the control stream of a process so that the processor can

271060

Contextual Info: Ä ß M Ä K K S B D M F @ B IM T rD 0 W in te l 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military High-Performance Embedded Architecture — 25 MIPS Burst Execution at 20 MHz — 9.4 MIPS* Sustained Execution at

Contextual Info: intei 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military On-Chip Memory Management Unit — 4 Gigabyte Virtual Address Space per Task — 4 Kbyte Pages with Supervisor/User Protection High-Performance Embedded

a4490

Abstract: 80960MC LAD12 80960KA 80960KB M8259A i960 mc errata
Contextual Info: PRELIMINARY 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Commercial • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ On-Chip Floating Point Unit

Power Supply Supervisor iw 1688

Abstract: 754for
Contextual Info: intei 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Commercial • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ On-Chip Floating Point Unit

80960MC

Abstract: branch conditional unconditional instruction
Contextual Info: Instruction-Set Summary Q CHAPTER 6 INSTRUCTION-SET SUMMARY This chapter provides an overview of the instruction set for the 80960MC processor. Included is a discussion of the instruction format and a summary of the instruction groups and the instructions in each group.

80960MC

Contextual Info: Data Types and Addressing Modes 5 CHAPTER 5 DATA TYPES AND ADDRESSING MODES This chapter describes the data types that the 80960MC processor recognizes and the address­ ing modes that are available for accessing memory locations. DATA TYPES The processor defines and operates on the following data types:

80960MC

Abstract: AD30 M82965 FFFC0000
Contextual Info: Initialization CHAPTER 14 INITIALIZATION This chapter describes the hardware requirements for initializing the 80960MC processor and the BXU in a fault-tolerant system design. The basic minimum initialization requirements are described, as well as some of the available options. The exact initialization procedure depends on the type of