82596SX Search Results

Bck 2801

Abstract: TB 2929 H alternative 0/TRANSFORMER bck 2801 10BASE2 10BASE5 386TM 82596DX 82596SX intel DOC 10Broad36
Contextual Info: 82596DX AND 82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting ■ Supports Industry Standard LANs — IEEE TYPE 10BASE-T (TPE),

dsc 8d15

Contextual Info: 82596DX AND 82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting ■ Supports Industry Standard LANs — IEEE TYPE 10BASE-T (TPE),

ku INTEL

Abstract: INTEL CORPORATION 29021 IEEE bus data 6
Contextual Info: inlel P f ö K L O G Ü f lO IM ß W 82596DX AND 82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting — HDLC Frame Delimiting

example manchester

Abstract: 82521TA 82596CA 82596DX 82596SX txc 20MHz
Contextual Info: PRBy&flONÂimr Intel* 82521TA TWISTED PAIR ETHERNET* SERIAL SUPERCOMPONENT Directly Interfaces Intel Ethernet LAN Controllers — 82586 — 82590 — 82592 — 82596SX, 82596DX, 82596CA No Configuration or Adjustment Required Satisfies FCC Class A Standards FCC

Contextual Info: in te i 82596DX AND 82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Perform s Com plete C SM A/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting — HDLC Frame Delimiting High-Performance 16-/32-B it Bus

scr tic 1160

Abstract: Cote Micro Technique 01BS2
Contextual Info: in t é l 82596DX AND 82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting Supports Industry Standard LANs — IEEE TYPE 10BASE-T (TPE),

INTEL I386

Abstract: 10BASE2 10BASE5 82596DX 82596SX CRC-32 LFSR 10Broad36 SX310
Contextual Info: 82596DX AND 82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR Y Performs Complete CSMA CD Medium Access Control MAC Functions Independently of CPU IEEE 802 3 (EOC) Frame Delimiting Y Supports Industry Standard LANs IEEE TYPE 10BASE-T (TPE) IEEE TYPE 10BASE5 (Ethernet )

Contextual Info: in te i 82596DX AND 82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR Perform s C om plete C S M A /C D Medium Access Control MAC Functions— Independently o f CPU — IEEE 802.3 (EOC) Fram e Delimiting Supports Industry Standard LANs — IEEE TYPE 10BASE-T (TPE),

Contextual Info: ¡n ie l 82596DX AND 82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting — HDLC Frame Delimiting Supports Industry Standard LANs

Contextual Info: 82596DX AND 82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting — HDLC Frame Delimiting ■ Supports Industry Standard LANs

TB 2929 H alternative

Contextual Info: 82596DX AND 82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting ■ Supports Industry Standard LANs — IEEE TYPE 10BASE-T (TPE),

ethernet mac TO HDLC

Abstract: 29021 Bck 2801
Contextual Info: inte P^IlLlMIQMÂtËSV 82596DX AND 82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR High-Performance 32-Bit Bus Master Interface — 66-MB/s Bus Bandwidth — 33-MHz Clock, Two Clocks Per Transfer — Bus Throttle Timers — Transfers Data at 100% of Serial

h2596

Abstract: SC25D 596S SC-25D
Contextual Info: in te i 82596DX AND 82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting — HDLC Frame Delimiting ■ Supports Industry Standard LANs

DP83932

Abstract: EISA9032 lh 9032 intel 82596 fci dh 22 T35 12H ix031 LA23-LA13 9010 plx LHi 954
Contextual Info: EISA 9032 T •CHNOLOBV^ EISA Bus Master Interface Chip Intel 82596 Mode APRIL 1993 Patent Pending_ Features_ General Description_ • EISA Bus Master Interface Chip containing all The EISA 9032 is an EISA bus master chip which can be

"network interface controller"

Abstract: intel 82596
Contextual Info: P L X TECHNOLOGY CORP MbE D • bôSSlMT ODOGISb S H P L X 7=52-33-55 T ■ C H N BUS MASTER INTERFACE ICs PRODUCT DESCRIPTION GUIDE September 1991 PLX Technology, Inc., 1991 PLX Technology, Inc., 625 Clyde Avenue, Mountain View, CA 94043 415 960-0448 FAX (415) 960-0479

9020

Abstract: intel 82596
Contextual Info: P L X TECHNOLOGY CORP 32E D • böSSm^ Q DD Q1 37 T *P L X T -5 2 -3 3 -5 5 EISA 9020 T ■ C H N O L O O V S' EISA Bus Master interface Chip for Intel 82596 LAN Controller Preliminary DECEMBER 1990 Features General Description EISA Bus Master Interface for

ZX-01

Abstract: T48I QD004
Contextual Info: P L X TECHNOLOGY CORP SSE D • bfi5514R D00ÜM13 'ÎSE mPLX EISA 9020BV T T 5 2 . '3 3 - 5 5 EISA Bus Master Interface Chip fo r Intel 82596 LAN Controller APRIL 1992 Patent Pending_ Features_ General Description_

T76B

Abstract: nad 116 intel 82596 CA1X 00D050 microchannel 1391P
Contextual Info: P L X TECHNOLOGY CORP S2E » • b asim i 0 0 Q 0 4 ÔÔ asa » p l x MC 9020 December 1991 Micro Channel Bus Master Interface Chip _ for Intel 82596 Ethernet Controller " r -S :x ~ 3 3 -S > S Features_ General Description_

82395DX

Abstract: 82395 80287 coprocessor architecture CA 5668 5665IN bem 69a ir 548h 82396sx
Contextual Info: in te i 82396SX SMART CACHE Optim ized ln te l 3 8 6 TM SX M icroprocessor Com panion Integrated 16 KB Data RAM 16-Byte Line Size 4 Way SET Associative w ith Pseudo LRU A lgorithm W rite B u ffe r A rch itectu re Dual Bus A rchitecture — Snooping M aintains Cache

RJ 45 ISO 8877

Abstract: 82521TB 82592 29025 1cdt
Contextual Info: [ p f ô iy O Ü ÏI D I M G W I n t e l' 82521TB TWISTED PAIR ETHERNET* SERIAL SUPERCOMPONENT Provides Complete Serial and Analog Twisted Pair Ethernet Interface — Analog Filters — Serial Interface and Transceiver — Manchester Encoder and Decoder — Link Integrity

H 9032

Abstract: SA3000
Contextual Info: EISA 9032 T% APRIL 1993 EISA Bus Master Interface Chip Intel 82596 Mode Patent Pending_ Features_ General Description_ * EISA Bus Master Interface Chip containing all The EISA 9032 is an EISA bus master chip which can be

82596dx

Abstract: 29022
Contextual Info: PRBOifflONMV Intel* 82521TA TWISTED PAIR ETHERNET* SERIAL SUPERCOMPONENT Provides Complete Serial and Analog Twisted Pair Ethernet Interface — Analog Filters — Serial Interface and Transceiver — Manchester Decoder — Isolation Transformers — Protection Circuitry

82596-PORT

Abstract: 9020 ttl AT9020 B3551 intel bios chip 8 pin detail
Contextual Info: P L X TECHNOLOGY C0RP SEE D • bôssm s 00003öS Ibfl H P L X AT 9020 NOVEMBER 1991 AT ISA Bus Master Interface Chip _for Intel 82596 Ethernet Controller 1 ^ 5 ^ -3 3 -3 5 Features_ General Description_

GD404

Abstract: A23-A17 intel bios chip 8 pin detail 9020
Contextual Info: P L X TECHNOLOGY SEE CORP bflssm s D 00003ÖS I b ê IPLX AT 9020 T a CHNOL O 0 V AT ISA Bus Master Interface Chip for Intel 82596 Ethernet Controller NOVEMBER 1991 • ^ -5 ^ -3 3 -3 5 General Description Features The AT 9020 is designed to provide the most compact,