84 PIN PLCC LATTICE DIMENSION Search Results

plsi1016

Abstract: 1016j ispLSI1016 1016E
Contextual Info: Lattice* ispLSI andpLSI 1016E “ ; Semiconductor •■■Corporation High-Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs — 96 Registers — High-Speed Global Interconnect

Contextual Info: Lattice* ispLSI andpLSI 1016E “ ; Semiconductor •■■Corporation High-Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs — 96 Registers — High-Speed Global Interconnect

Contextual Info: Lattice Features ispLSr and pLSI 2032 High Density Programmable Logic Functional Block Diagram HIGH DENSITY PROGRAMMABLE LOGIC — — — — — 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State

DS-0067

Contextual Info: Latticei ; Semiconductor i Corporation Features ispLSI' and pLSI' 2032 High Density Programmable Logic Functional B lock Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers High Speed Global Interconnect

Contextual Info: I ha ftir p C I H I w !L is p L S 1 1 0 3 2 in-system programmable Large Scale Integration High-Density Programmable Logic Functional Block Diagram Features IN-SYSTEM PROGRAMMABLE HIGH-DENSITY LOGIC — Member of Lattice’s ispLSI Family — Fully Compatible with Lattice's pLSP Family

1032E

Contextual Info: Lattice' ispLSI and pLSI 1032E | Semiconductor I Corporation High-Density Programmable Logic Functional Block Diagram Features • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — High Speed Global Interconnect

pLS11032E

Contextual Info: Lattice' ispLSI and pLSI 1032E | Semiconductor I Corporation High-Density Programmable Logic Functional Block Diagram Features • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — High Speed Global Interconnect

Contextual Info: «P° «S 199? 1032 pLSI Lattine V i &« I w W programmable Large Sea Scale Integration Features Functional Block Diagram • PROGRAMMABLE HIGH DENSITY LOGIC — — — — — Member of Lattice’s pLSI Family High Speed Global Interconnects 64 I/O Pins, Eight Dedicated Inputs

Contextual Info: APR 2 2 ¡993 p L S f 1032 programmable Large Scale Integration High-Density Programmable Logic Functional Block Diagram Features • PROGRAMMABLE HIGH-DENSITY LOGIC ETPE1 FTTH rTW l i l l — — — — — Member of Lattice’s pLSI Family High-Speed Global Interconnects

isplsi device layout

Contextual Info: 2 2 1993 in-system programmable Large Scale Integration High-Density Programmable Logic Functional Block Diagram Features • IN-SYSTEM PROGRAMMABLE HIGH-DENSITY LOGIC — Member of Lattice’s ispLSI Family — Fully Compatible with Lattice's pLSI Family

Contextual Info: APR 6 1992 I a %t tUir p !& • ! W w ispLSr 1032 in-system programmable Large Scale Integration Features Functional Block Diagram • in-system programmable HIGH DENSITY LOGIC TH — — — — — — Member of Lattice’s ispLSI Family Fully Compatible with Lattice's pLSI Family

84 pin plcc lattice dimension

Abstract: C045
Contextual Info: Package Diagrams November 2003 16-Pin Plastic DIP Package Dimensions in Inches -BN/2 b1 1 WITH LEAD FINISH E 5 6 CL E1 c1 c N SEE DETAIL A BASE METAL (b) SECTION Z-Z CL BASE PLANE c 5 -A- D 6 eA Z Z 4 A2 A eB 7 -C.015 SEATING PLANE A1 L b2 10 b .010 GAGE

Contextual Info: Lattice T'Aie Lattice ispLSI and pLSI 2000 Family ï i I Corporation Features_ J Introduction to ispLSI and pLSI 2000 Family ispLSI and pLSI 2000 Family □ 154 M Hz System Perform ance □ 5.5 ns Pin-to-Pin Delay □ High Density 1,000-6,000 PLD Gates

AL048

Contextual Info: 4bE D LATTICE SEMICON DUC TOR iiiLattice m SaôbTMS 0001434 a B ILAT p L S r 1032 programmable Large Scale Integration _ Pft'-/Ÿ-OŸ •■■■■■ m mfn • PROGRAMMABLE HIGH DENSITY LOGIC I — fmax = 80 MHz Maximum Operating Frequency — tpd = 15 ns Propagation Delay

Contextual Info: pLSr 1032 Lattice programmable Large Scale Integration Functional Block Diagram Features • PROGRAMMABLE HIGH DENSITY LOGIC — — — — — Member of Lattice’s pLSI Family High Speed Global Interconnects 64 I/O Pins, Eight Dedicated Inputs 192 Registers

Contextual Info: LATTICE SEMICONDUCTOR 4bE D il a t t ir p mL a C l « l i I w • SBfibTHT OÜOlMûb S ■ LAT pLSr 1024 w program m able Large Scale Integration : : : : T - v é - z i- ô « ? — Functional Block? Diagram* ¿m □ • PROGRAMMABLE HIGH DENSITY LOGIC — Member of Lattice’s pLSI Family

Contextual Info: l a tt ic e sem ico nducto r 4bE D • SBAfalMI G Q D m m h BILAT p L S r 1016 ü lL a ttic e programmable Large Scale Integration T -Ÿ é /' Ÿ Û ' wu.»ir.q r j ^ ■ ä ü ä a a iü ä Feature Ÿ a • PROGRAMMABLE HIGH DENSITY LOGIC —• Member of Lattice's pLSI Family

Contextual Info: LATTICE SEMIC ON DU CT OR 4bE D 536 ^4=1 aQQlSb2 b » L A T ispLS r 1016 illL a ìtic e in*system programmable Large Scale Integration •■■■I Feature ■ - 7~?é~ff-07 iiOam Functional Block; Diagrarri'»^^- m • In-system programmable HIGH DENSITY LOGIC

gal programmer

Abstract: TCO-214 isplsi1016 opa 2143
Contextual Info: 4LE D LATTICE SEMICO ND UCTOR ispLSr 1016 ü iL a ttic e in*system programmable Large Scale Integration •■■■I Feature 536^4= 1 GQOlShE b « L A T - 7 ^ ? é ~ i? -0 7 7"e73 iiOam

16MM TAPE PACKAGE

Contextual Info: Tape-and-Reel Specifications Introduction Lattice’s Tape-and-Reel Procedures A tape-and-reel packing container is available for plastic leaded chip carriers PLCC , small outline integrated circuits (SOIC), shrunk small outline packages (SSOP) and thin quad flat pack (TQFP) packages to protect the

Contextual Info: Lattice* “ ; Semiconductor ispLSI and pLSI 2064 •■■Corporation High Density Programmable Logic Functional Block Diagram Features • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — 2000 PLD Gates 64 I/O Pins, Four Dedicated Inputs 64 Registers

Contextual Info: I attipp IL a C l H I U ispLSr 1032 in-systsm programmable Large Scale Integration Functional Block Diagram Features • In-system programmable HIGH DENSITY LOGIC — Member of Lattice's IspLSI Family — Fully Compatible with Lattice's pLSI Family — High Speed Global Interconnects

Contextual Info: ispLSr 1032 lü L a tlic e in-system programmable Large Scale Integration •■■■■■ LATTICE SEMICONDUCTOR m BM FZ, r -r - n ìfi OQQlSSfl b H L A T 4bE D r r ^ w ^ a a iis * 1 Functional BiocfC Diagramp- m i • in-system programmable HIGH DENSITY LOGIC

ltls

Abstract: C1991 LYPR ispLS11048 SAAB
Contextual Info: ispLSr 1032 ; ! ! L •■■■■■ a L A T T IC E î î ï S in-systsm programmable Large Scale Integration 3 SE M IC O N D U C T O R U S m qfm Q ur M LiE s a a b ' m Qooisaa h * l a t D Functional BiocfC Diagramp- mi • In-system programmable HIGH DENSITY LOGIC