840MBPS Search Results

Contextual Info: BurrĆBrown Products from Texas Instruments ADS5242 SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 4-Channel, 12-Bit, 65MSPS Analog-to-Digital Converter with Serial LVDS Interface FEATURES • • • • • • • • • • • • • • Maximum Sample Rate: 65MSPS

Contextual Info: BurrĆBrown Products from Texas Instruments ADS5242 SBAS330B – OCTOBER 2004 – REVISED SEPTEMBER 2005 4-Channel, 12-Bit, 65MSPS Analog-to-Digital Converter with Serial LVDS Interface FEATURES • • • • • • • • • • • • • • Maximum Sample Rate: 65MSPS

ADS5270

Abstract: ADS5270IPFP ADS5271 ADS5272 ADS5273 ADS5277
Contextual Info: ADS5270 www.ti.com. SBAS293F – JANUARY 2004 – REVISED JANUARY 2009 8-Channel, 12-Bit, 40MSPS Analog-to-Digital Converter

Contextual Info: BurrĆBrown Products from Texas Instruments ADS5242 SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 4-Channel, 12-Bit, 65MSPS Analog-to-Digital Converter with Serial LVDS Interface FEATURES • • • • • • • • • • • • • • Maximum Sample Rate: 65MSPS

DS90C124

Contextual Info: DS90C241 Serializer and DS90C124 Deserializer Evaluation Kit User’s Manual NSID: SERDES24-35USB Rev 1.5 National Semiconductor Corporation Date: 2/27/2008 Page 1 of 39 Table of Contents TABLE OF CONTENTS . 2

Contextual Info: ADS5277 www.ti.com. SBAS333D – FEBRUARY 2005 – REVISED JANUARY 2009 8-Channel, 10-Bit, 65MSPS Analog-to-Digital Converter

Implementation of digital clock using flip flops

Abstract: ffts used in software defined radio Lattice Semiconductor Package Diagrams 256-Ball fpBGA
Contextual Info: Expanding Applications For Low Cost FPGAs A Lattice Semiconductor White Paper April 2007 Revised August 2007 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: 503 268-8000 www.latticesemi.com 1 Expanding Applications For Low Cost FPGAs

MAX9217

Abstract: MAX9247 MAX9248 MAX9250
Contextual Info: 19-3943; Rev 3; 4/09 KIT ATION EVALU LE B A IL A AV 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is

Crossbar Switches

Contextual Info: 19-4215; Rev 2; 4/11 KIT ATION EVALU E L B AVAILA Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches Features The MAX9132/MAX9134/MAX9135 high-speed, multiple-port, low-voltage differential signaling LVDS crossbar switches are specially designed for digital video

Broken Conductor Detection for Overhead Line Distribution System

Abstract: verilog code for CORDIC to generate sine wave verilog code for cordic algorithm for wireless la TXC 13.56 sma diode h5c intel 945 motherboard schematic diagram 2005Z fet k241 EARTH LEAKAGE RELAY diagram schematic diagram for panasonic inverter air cond
Contextual Info: Stratix GX Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 www.altera.com SGX5V1-1.2 Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

Contextual Info: 19-4215; Rev 0; 7/08 Programmable, High-Speed, Multiple Input/Output LVDS Crossbar Switches Features The MAX9132/MAX9134/MAX9135 high-speed, multiple-port, low-voltage differential signaling LVDS crossbar switches are specially designed for digital video

Contextual Info: 19-3943; Rev 1; 8/06 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take

Contextual Info: 19-3955; Rev 4; 4/12 KIT ATION EVALU E L B A AVAIL 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer Features ♦ Preemphasis Improves Eye Diagram and Signal Integrity at the Output ♦ Proprietary Data Encoding for DC Balance and Reduced EMI ♦ Control Data Sent During Video Blanking

B17C

Abstract: teradyne flex tester AGX52001-1 AGX52002-1 AGX52003-1 AGX52004-1 AGX52005-1 AGX52006-1 AGX52007-1 AGX52008-1
Contextual Info: Arria GX Device Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 www.altera.com AGX5V2-1.2 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

Contextual Info: BurrĆBrown Products from Texas Instruments ADS5277 SBAS333C – FEBRUARY 2005 – REVISED SEPTEMBER 2005 8-Channel, 10-Bit, 65MSPS Analog-to-Digital Converter with Serial LVDS Interface FEATURES The ADS5277 provides internal references, or can optionally be driven with external references. Best

EP20K1000C

Abstract: EP20K100E EP20K200C EP20K30E EP20K400C EP20K600C EP20K60E APEX 20ke development board sram apex ep20k400 sopc development board APEX 20ke development board sram pin assignments
Contextual Info: APEX Devices High-Density Embedded Programmable Logic Devices for System-Level Integration 0KC 2 X E AP eaturing F r Coppe r e y a All-L onnect Interc July 2002 APEX programmable logic devices provide the flexibility and high density needed for system-on-a-programmable-chip SOPC

945 MOTHERBOARD pcb CIRCUIT diagram

Abstract: VCO 1.4 GHz
Contextual Info: Using High-Speed I/O Standards in APEX II Devices August 2002, ver. 1.7 Introduction Application Note 166 Recent expansion in the telecommunications market and growth in Internet use have created a demand to move more data faster than ever. To meet this demand, system designers are relying on solutions such as

DDR RAM 512M

Contextual Info: White Paper アルテラの PLD による QoS 機能の実現方法 イントロダクション インターネット・プロトコル（IP）ネットワークは従来から提供されている e-mail、web ブラウジング、あるいはファイ

Contextual Info: ADS5272 www.ti.com. SBAS324C – JUNE 2004 – REVISED JANUARY 2009 8-Channel, 12-Bit, 65MSPS ADC with Serial LVDS Interface

altera stratix II fpga

Abstract: EPCS16 EPCS64 SSTL-18 18x18-Bit
Contextual Info: White Paper Architectural Differences Between Stratix II and Stratix Devices Introduction Stratix II devices, Altera's next-generation high-density FPGAs, are based on the award-winning Stratix device architecture. Building on the innovations that made Stratix FPGAs an instant success, Stratix II devices provide new

Contextual Info: 19-3955; Rev 4; 4/12 KIT ATION EVALU E L B A AVAIL 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer Features ♦ Preemphasis Improves Eye Diagram and Signal Integrity at the Output ♦ Proprietary Data Encoding for DC Balance and Reduced EMI ♦ Control Data Sent During Video Blanking

MAX9218

Abstract: MAX9247
Contextual Info: 19-3955; Rev 3; 4/09 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer Features ♦ Preemphasis Improves Eye Diagram and Signal Integrity at the Output ♦ Proprietary Data Encoding for DC Balance and Reduced EMI ♦ Control Data Sent During Video Blanking

Contextual Info: ADS5271 AD S 52 71 www.ti.com. SBAS313C – JUNE 2004 – REVISED JANUARY 2009 8-Channel, 12-Bit, 50MSPS Analog-to-Digital Converter

1024LSB

Abstract: ADS5270 ADS5271 ADS5272 ADS5273 ADS5277 ADS5277IPFP
Contextual Info: ADS5277 www.ti.com. SBAS333D – FEBRUARY 2005 – REVISED JANUARY 2009 8-Channel, 10-Bit, 65MSPS Analog-to-Digital Converter