F100K
Abstract: SY100S314 SY100S314FC SY100S314JC SY100S314JCTR
Text: QUINT DIFFERENTIAL LINE RECEIVER FEATURES SY100S314 DESCRIPTION • Max. propagation delay of 900ps ■ Differential outputs ■ IEE min. of –60mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved
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SY100S314
900ps
F100K
24-pin
28-pin
SY100S314
SY100S314FC
F24-1
SY100S314JC
J28-1
F100K
SY100S314FC
SY100S314JC
SY100S314JCTR
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4.2V
Abstract: and gate d3c F100K SY100S317 SY100S317FC SY100S317JC SY100S317JCTR
Text: TRIPLE 2-WIDE OA/OAI GATE FEATURES SY100S317 FINAL DESCRIPTION • Max. propagation delay of 900ps ■ IEE min. of –48mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved noise immunity ■ Internal 75KΩ input pull-down resistors
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SY100S317
900ps
F100K
24-pin
28-pin
SY100S317
CONFIGURA0S317FC
F24-1
SY100S317JC
J28-1
4.2V
and gate d3c
F100K
SY100S317FC
SY100S317JC
SY100S317JCTR
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Untitled
Abstract: No abstract text available
Text: TRIPLE 2-WIDE OA/OAI GATE Micrel, Inc. FEATURES SY100S317 SY100S317 DESCRIPTION • Max. propagation delay of 900ps ■ IEE min. of –48mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved noise immunity
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SY100S317
900ps
F100K
28-pin
SY100S317
M9999-042307
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MAX9316
Abstract: MAX9322 MAX9322ECY MAX9322ETK
Text: 19-2544; Rev 0; 7/02 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver Applications Features ♦ 1.2ps RMS Maximum Random Jitter ♦ 300mV Differential Output at 1.0GHz ♦ 900ps Propagation Delay ♦ Selectable Divide-by-1 or Divide-by-2 Frequency
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300mV
900ps
MAX9322ECY
MAX9322ETK*
MAX9322
MAX9316
MAX9322
MAX9322ECY
MAX9322ETK
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Marking D1c
Abstract: F100K SY100S317 SY100S317JC SY100S317JCTR
Text: TRIPLE 2-WIDE OA/OAI GATE Micrel, Inc. FEATURES SY100S317 SY100S317 DESCRIPTION • Max. propagation delay of 900ps ■ IEE min. of –48mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved noise immunity
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SY100S317
900ps
F100K
28-pin
SY100S317
M9999-042307
Marking D1c
F100K
SY100S317JC
SY100S317JCTR
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Untitled
Abstract: No abstract text available
Text: * QUINT DIFFERENTIAL LINE RECEIVER SYNERGY SY100S314 SEMICONDUCTOR DESCRIPTION FEATURES • Max. propagation delay of 900ps ■ Differential outputs ■ Ie e min. o f-60m A ■ ESD protection of 2000V ■ Extended supply voltage option: — VEE = -4.2V to -5.46V
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SY100S314
900ps
f-60m
F100K
SY100S314
SY100S314DC
D24-1
SY100S314FC
F24-1
SY100S314JC
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Untitled
Abstract: No abstract text available
Text: * SYNERGY 12-BIT PARITY GENERATOR/CHECKER SY10E160 SY100E160 SEMICONDUCTOR DESCRIPTION FEATURES Provides odd-HIGH parity of 12 inputs Extended 100E Vee range of -4.2V to -5.5V Output register with Shift/Hold capability 900ps max. D to QId output Enable control
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12-BIT
SY10E160
SY100E160
900ps
MC10E/100E160
28-pin
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Untitled
Abstract: No abstract text available
Text: « HEX D-LATCH SYNERGY SY100S350 SEMICONDUCTOR DESCRIPTION FEATURES • Max. transparent propagation delay of 900ps ■ Min. Master Reset and Enable pulse widths of 100ps ■ I ee mln. of -98m A ■ ESD protection of 2000V ■ Industry standard 100K ECL levels
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SY100S350
900ps
100ps
SY100S350
propagatio1000
TDG13Ã
SY100S350DC
D24-1
SY100S350FC
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Untitled
Abstract: No abstract text available
Text: « SYNERGY SEMICONDUCTOR DUAL 8-INPUT MULTIPLEXER FEATURES SY100S363 DESCRIPTION Max. propagation delay of 900ps The S Y 100S 363 is a d u a l 8 -in p u t m u ltip le xe r designed fo r use in new, h ig h -p e rfo rm a n c e ECL system s. The th re e D ata S e le ct inputs So, S i, S 2 d e te rm in e the bits
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SY100S363
900ps
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Untitled
Abstract: No abstract text available
Text: « SYNERGY HEX D-LATCH SY100S350 SEMICONDUCTOR FEATURES • Max. transparent propagation delay of 900ps ■ Min. Master Reset and Enable pulse widths of 100ps ■ Ie e min. of -98m A ■ Industry standard 100K ECL levels ■ Extended supply voltage option:
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SY100S350
900ps
100ps
SY100S350
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5a6v
Abstract: F100K SY100S350 SY100S350DC SY100S350FC SY100S350JC
Text: * HEX D-LATCH SYNERGY SY100S350 S E M IC O N D U C TO R D E S C R IP T IO N FEATURES • Max. transparent propagation delay of 900ps ■ Min. Master Reset and Enable pulse widths of 100ps ■ I e e mln. of -98m A ■ ESD protection of 2000V ■ Industry standard 100K ECL levels
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SY100S350
900ps
100ps
-98mA
F100K
SY100S350
SY100S350DC
D24-1
SY100S350FC
5a6v
F100K
SY100S350JC
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d1996
Abstract: F100K SY100S314 SY100S314DC D15F
Text: « QUINT DIFFERENTIAL LINE RECEIVER SYNERGY SEMICONDUCTOR FEATURES • ■ Max. propagation delay of 900ps ■ Differential outputs ■ I e e min. of -60m A ■ ESD protection of 2000V ■ Extended supply voltage option: V ee = -4.2V to -5.5V ■ Voltage and temperature compensation for
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SY100S314
900ps
-60mA
F100K
SY100S314
SY100S314DC
D24-1
SY100S314FC
F24-1
SY100S314JC
d1996
F100K
D15F
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F100K
Abstract: SY100S363
Text: * DUAL 8-INPUT MULTIPLEXER SYNERGY SEMICONDUCTOR FEATURES • ■ Max. propagation delay of 900ps ■ I e e min. of -92mA ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option: — VEE = -4.2V to -5.46V ■ Voltage and temperature compensation for
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SY100S363
900ps
-92mA
F100K
SY100S363
F100K
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Untitled
Abstract: No abstract text available
Text: * SYNERGY SEMICONDUCTOR 12-BIT PARITY G ENERA TO R/CHECKER DESCRIPTION FEATURES Provides odd-HIGH parity of 12 inputs Extended 100E V ee range of -4.2V to -5.5V Output register with Shift/Hold capability 900ps max. D to Q/Q output Enable control Asynchronous Register Reset
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12-BIT
SY10E160
SY100E160
900ps
MC10E/100E160
28-pin
018-Mot
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Untitled
Abstract: No abstract text available
Text: * SYNCHGY SEMICONDUCTOR DUAL 8-INPUT MULTIPLEXER FEATURES Max. propagation delay of 900ps Iee min. o f-92 m A Industry standard 100K ECL levels Extended supply voltage option: V ee = -4.2V to -5.5V Voltage and temperature compensation for improved noise immunity
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OCR Scan
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PDF
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900ps
SY100S363
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Untitled
Abstract: No abstract text available
Text: * TRIPLE 2-WIDE OA/OAI GATE SYNERGY SY100S317 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 900ps Iee min. o f-48 m A Extended supply voltage option: V ee = -4.2V to -5.5V The S Y 100S 317 is a set of ultra-fast, triple 2-w ide OR/ AND gates designed for use in high-perform ance ECL
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SY100S317
900ps
75Ki2
F100K
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Untitled
Abstract: No abstract text available
Text: * SYNERGY SY10E156 SY100E156 3-BIT 4:1 MUX-LATCH SEMICONDUCTOR DESCRIPTION FEATURES • 900ps max. D to output ■ Extended 100E V ee range of -4.2V to -5.5V ■ 800ps max. LEN to output ■ Differential outputs ■ Asynchronous Master Reset ■ Dual latch enables
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SY10E156
SY100E156
900ps
800ps
MC10E/100E156
28-pin
SY10/100E156
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Untitled
Abstract: No abstract text available
Text: * 12-BIT PARITY GENERATOR/CHECKER SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • ■ ■ ■ ■ ■ ■ ■ Provides odd-HIGH parity of 12 Inputs Output register with Shift/Hold capability 900ps max. D to Q/Q output Enable control Asynchronous Register Reset
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12-BIT
SY10E160
SY100E160
900ps
MC10E/100E160
SY10E160
SY100E160
12-bit
SY10E160JC
J28-1
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Untitled
Abstract: No abstract text available
Text: * SYNERGY SY10E156 SY100E156 3-BIT 4:1 MUX-LATCH SEMICONDUCTOR DESCRIPTION FEATURES • 900ps max. D to output ■ Extended 100E V ee range of -4.2V to -5.5V ■ 800ps max. LEN to output ■ Differential outputs ■ Asynchronous Master Reset ■ Dual latch enables
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SY10E156
SY100E156
900ps
800ps
MC10E/100E156
28-pin
SY10/100E156
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F100K
Abstract: SY100S317 SY100S317DC SY100S317FC ez 623
Text: « Ä TRIPLE 2-WIDE OA/OAi g a t e SYNERGY s y io o s 317 SE M IC O N D U C TO R FEATURES DESCRIPTION I Max. propagation delay of 900ps The S Y 100S 317 is a set of ultra-fast, triple 2-w ide OR/ AND gates designed for use in high-perform ance ECL system s. T his device offers both true and com plem ent
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SY100S317
900ps
-48mA
F100K
D00E173
SY100S317DC
D24-1
SY100S317FC
F24-1
F100K
SY100S317
ez 623
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Untitled
Abstract: No abstract text available
Text: * A i# iie i /« |/ SYNCHGY SEMICONDUCTOR DUAL 8-INPUT MULTIPLEXER FEATURES Max. propagation delay of 900ps Iee min. o f-92 m A Industry standard 100K ECL levels Extended supply voltage option: V ee = -4.2V to -5.5V Voltage and temperature compensation for
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OCR Scan
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PDF
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SY100S363
900ps
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Untitled
Abstract: No abstract text available
Text: * SYNERGY SY10E156 SY100E156 3-BIT 4:1 MUX-LATCH SEMICONDUCTOR DESCRIPTION FEATURES • 900ps max. D to output ■ Extended 100E V ee range of -4.2V to -5.5V ■ 800ps max. LEN to output ■ Differential outputs ■ Asynchronous Master Reset ■ Dual latch enables
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OCR Scan
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SY10E156
SY100E156
900ps
800ps
MC10E/100E156
28-pin
SY10/100E156
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Untitled
Abstract: No abstract text available
Text: S YN ER G Y S E M IC O N D U C T O R F EA TU R E S Max. transparent propagation delay of 900ps Min. Master Reset and Enable pulse widths of lOOps I ee min. of -98mA Industry standard 100K ECL levels Extended supply voltage option: Vee = -4.2V to -5.5V Voltage and temperature compensation for
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OCR Scan
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900ps
-98mA
75Ki2
F100K
24-pin
28-pin
SY100S350
SY100S350
350FC
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Untitled
Abstract: No abstract text available
Text: <o> SYNERGY ]- BI T 4 î M U X :>v t LATCH ö l 155 •; Y 1 0 0 E 1 5 6 S E M IC O N D U C T O R DESCRIPTION FEATURES ■ 900ps max. D to output ■ Extended 100E Vee range of -4.2V to -5.5V ■ 800ps max. LEN to output ■ Differential outputs ■ Asynchronous Master Reset
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900ps
800ps
MC10E/100E156
28-pin
Y10/100E156
SY10E156JC
SY10E156JCTR
SY100E156JC
SY100E156JCTR
J28-1
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