99040 Search Results

philips tea 1090

Abstract: 6880H Murata SFr 450 filter ic tea 1090 saa7709 SAA 7709 h philips SAA7709 fm transmitter 5km SAA 7709 Murata sfr450h
Contextual Info: APPLICATION NOTE AN 99040 TEA684x FAMILY A NICE RADIO FOR NEW IN CAR ENTERTAINMENT Version 2.0 1 TEA 6840H A NICE RADIO for New In Car Entertainment APPLICATION NOTE AN 99040 Abstract The IC TEA 6840 and its derivative versions TEA 6845 / 6846 are for small

SAA7709

Abstract: philips SAA7709 Murata SFr 450 filter fm transmitter 5km 6880H philips tea 1090 ic tea 1090 a952 Murata sfr450h smd 5VOLT AUDIO AMPLIFIER IC
Contextual Info: APPLICATION NOTE AN 99040 TEA684x FAMILY A NICE RADIO FOR NEW IN CAR ENTERTAINMENT Version 1.0 1 TEA 6840H A NICE RADIO for New In Car Entertainment APPLICATION NOTE AN 99040 Abstract The IC TEA 6840 and its derivative versions TEA 6845 / 6846 are for small

Contextual Info: ArcticLink III BX6 Solution Platform Data Sheet •••••• I2C Client Platform Highlights Serial Peripheral Interface SPI Master • CPU interface for configuring and controlling internal registers and look-up tables (LUT). NOTE: The MIPI interface can also be used instead

PA9540

Abstract: PA9540B
Contextual Info: PCA9540B 2-channel I2C-bus multiplexer Rev. 04 — 3 September 2009 Product data sheet 1. General description The PCA9540B is a 1-of-2 bidirectional translating multiplexer, controlled via the I2C-bus. The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels.

P8563

Abstract: NXP 8563T 8563t PCF8563T PCF8563P 8563S
Contextual Info: PCF8563 Real-time clock/calendar Rev. 10 — 3 April 2012 Product data sheet 1. General description The PCF8563 is a CMOS1 Real-Time Clock RTC and calendar optimized for low power consumption. A programmable clock output, interrupt output, and voltage-low detector are

lvds to mipi

Contextual Info: ArcticLink III VX5 Solution Platform Data Sheet •••••• High Definition Visual Enhancement Engine VEE HD+ and Display Power Optimizer (DPO HD+) Solution Platform Highlights High Definition Visual Enhancement Engine • VEE HD+ compensates for different viewing

bs415 250V

Abstract: CS222M BS415 EN132400 BS415 250V X1Y2 BS415 TJ508. 250V AC.250V TJ508 vde bs415 cs222m BS415 TJ508 CS11-E2GA222MYNS
Contextual Info: 1/2 Disk Ceramic Capacitors with Lead Safety Standard Approved CS Series BASIC INSULATION TYPE Temperature range: –25 to +125°C CLASS 2 HIGH DIELECTRIC FEATURES • Smaller than conventional capacitors. • Flame-resistant reinforced outer insulation prevents fires, electrical shock, and other potential hazards.

QL3004

Abstract: PLCC-84 QL3060 QL2003 QL2005 QL2007 QL2009 QL3012 QL3025 QL3040
Contextual Info: QuickSheet#4 pASIC FPGA Families High-Speed, Low Power, Instant-On, High Security FPGAs pASIC Family Highlights • High performance over 400 MHz • 100% routability and pin stability • Instant-On capability • High security and reliability • Low power

JESD22-A114

Abstract: JESD22-A115 JESD78 PCA9553 PCA9554 PCF8574
Contextual Info: PCA9553 4-bit I2C-bus LED driver with programmable blink rates Rev. 06 — 29 December 2008 Product data sheet 1. General description The PCA9553 LED blinker blinks LEDs in I2C-bus and SMBus applications where it is necessary to limit bus traffic or free up the I2C-bus master's MCU, MPU, DSP, chip set,

JESD22-A114

Abstract: JESD22-A115 JESD78 P82B96 PCA82C250 PCA9600 PCA9600D PCA9600DP
Contextual Info: PCA9600 Dual bidirectional bus buffer Rev. 04 — 11 November 2009 Product data sheet 1. General description The PCA9600 is designed to isolate I2C-bus capacitance, allowing long buses to be driven in point-to-point or multipoint applications of up to 4000 pF. The PCA9600 is a

JESD22-A114

Abstract: JESD22-A115 JESD78 P82B96 PCA82C250 PCA9600 PCA9600D PCA9600DP
Contextual Info: PCA9600 Dual bidirectional bus buffer Rev. 03 — 3 September 2009 Product data sheet 1. General description The PCA9600 is designed to isolate I2C-bus capacitance, allowing long buses to be driven in point-to-point or multipoint applications of up to 4000 pF. The PCA9600 is a

Contextual Info: V320USC Universal System Controller • • • • • • PCI System Controller for 32-Bit MIPS and SuperH™ System Interface Device Highlights Overview • Glueless interface between popular MIPS and SuperH processors and the standard 32-bit PCI bus

transistor SMD N02

Abstract: NVT2002DP NVT2002GD NVT2002GF NVT2002 JESD22-A114 JESD22-A115 NVT2001 NVT2001GM
Contextual Info: NVT2001; NVT2002 Bidirectional voltage level translator for open-drain and push-pull applications Rev. 1 — 30 August 2010 Product data sheet 1. General description The NVT2001/02 are bidirectional voltage level translators operational from 1.0 V to 3.6 V

NXP 8563T

Abstract: 8563T NXP 8563 rtc PCF8563 rtc ic 8563 PCF8563P 8563S smd transistor marking a2h NXP 8563T part marking rtc PCF8563 REV. 7
Contextual Info: PCF8563 Real-time clock/calendar Rev. 8 — 18 November 2010 Product data sheet 1. General description The PCF8563 is a CMOS1 Real-Time Clock RTC and calendar optimized for low power consumption. A programmable clock output, interrupt output, and voltage-low detector are

Contextual Info: V320USC Universal System Controller • • • • • • PCI System Controller for 32-Bit MIPS and SuperH™ System Interface Device Highlights Introduction • Glueless interface between popular MIPS™ and SuperH™ processors and the standard 32-bit PCI

PU86

Contextual Info: QuickLogic PolarPro Device Data Sheet — 86-Pin TFBGA QL1P100 •••••• Combining Low Power, Performance, Density, and Embedded RAM • Quadrant-based segmentable clock networks Device Highlights  16 quad clock networks per device Low Power Programmable Logic

Contextual Info: Eclipse II Family Data Sheet • • • • • • Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Multiple dedicated low skew clock networks Flexible Programmable Logic • High drive input-only networks

Contextual Info: QuickLogic PolarPro Data Sheet • • • • • • Combining Low Power, Performance, Density, and Embedded RAM Device Highlights  4 programmable global clock networks • Quadrant-based segmentable clock networks Low Power Programmable Logic  20 quad clock networks per device

I960JX v363epc

Abstract: 160-Pin Flat Package pci bridge V380SDC
Contextual Info: V363EPC Data Sheet • • • • • • V363EPC Local Bus to PCI Bridge for Embedded Processors Device Highlights • Direct interface to these processors: • Up to 50 MHz on both PCI and local bus clocks • 3.3 V operation; 5 V tolerant input • Industrial temperature range

ATM circuit diagram

Abstract: TC35821F
Contextual Info: TC358541F 155Mbps ATM SAR General Description Features The TC358541F chip has been designed for use in an Asynchronous Transfer Mode ATM User Network Interface (UNI). Packet stream to/from ATM link trough packet buffer, traffic shaping and buffer management per VP and VC basis, and full support

QL1P100

Contextual Info: QuickLogic PolarPro Device Data Sheet — QL1P075, QL1P100, QL1P200, and QL1P300 •••••• Combining Low Power, Performance, Density, and Embedded RAM • Quadrant-based segmentable clock networks Device Highlights  20 quad clock networks per device

Contextual Info: Eclipse II Family Data Sheet • • • • • • Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Multiple dedicated low skew clock networks Flexible Programmable Logic • High drive input-only networks

QUICKLOGIC SDIO Host

Contextual Info: PolarPro Solution Platform Family Data Sheet •••••• Family of Solution Platforms Integrating Low Power Programmable Fabric and Embedded SRAM Platform Highlights Flexible Programmable Fabric • 8 to 240 customizable building blocks CBBs (see

Contextual Info: QL58x0 Enhanced QuickPCI Target Family Data Sheet • • • • • • 33/66 MHz/32-bit PCI Target with Embedded Programmable Logic, Embedded Computational Units, and Dual Port SRAM Device Highlights Extendable PCI Functionality High Performance PCI Controller