A14IZ Search Results

LH53V4C00ET

Abstract: sharp mask rom 48-pin
Contextual Info: CMOS 4M 512K x 8/256K x 16 MROM FEATURES • 524,288 x 8 bit organization (Byte mode: BYTE = V,L) 262,144 x 16 bit organization (Word mode: BYTE = V,H) PIN CONNECTIONS 48-PIN TSOP (Type I) r TOP VIEW A15C 1 • A14IZ 2 A13C 3 • Access time: 150 ns (MAX.)

Contextual Info: Advance Data Sheet June 1992 ^ B A T s iT ^ ^ ^ M ic ro e le c tro n ic s ATT3000 Series Military Field-Programmable Gate Arrays Features • User-programmable gate array ■ Low-power, CMOS, static memory technology ■ Standard product; 100% factory tested

Contextual Info: IM P O R T A N T N O TIC E All new designs should use XC3000A or XC3100A. Information on XC3000 and XC3100 is presented here as reference for existing designs. £ x il in x XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Product Description

M3P1

Abstract: KD 2107 X3032
Contextual Info: XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families £ Product Description Features • Complete XACT Development System - Schematic capture, automatic place and route - Logic and timing simulation - Interactive design editor for design optimization

B1581

Abstract: B1379 bl238
Contextual Info: CMOS SyncBiFlFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2 • • • • • • • • • • FEATURES: • Free-running CLKA and CLKB can be asynchronous or coincident sim ultaneous reading and writing of data on a single clock edge is perm itted

ATT3000

Abstract: ATT3020
Contextual Info: AT&T Data Sheet July 1992 Microelectronics ATT3000 Series Field-Programmable Gate Arrays FEATURES • High Performance— up to 150 MHz Toggle Rates • User-Programmable Gate Array • I/O functions • Digital logic functions • Interconnections • Flexible array architecture

EFB01

Contextual Info: CMOS SyncBiFIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 1dt IDT723614 ìitegiatsd D ev±;e Technology, lie . FEATURES: • Free-running C LKA and CLKB can be asynchronous or coincident sim ultaneous reading and writing of data on a single clock edge is permitted)

Contextual Info: HM621664H/HM621864H Series 65536-word x 16/18-bit High Speed CMOS Static RAM HITACHI Description The HM621664H/HM621864H is an asynchronous high speed static RAM organized as 64-kword x 16/18bit. It realize high speed access time 20/25 ns with employing 0.8 |im CMOS process and high speed circuit

614l

Abstract: BNXXX
Contextual Info: CMOS SyncBiFlFO WITH BUS-MATCHING AND BYTE SWAPPING 64 X 36 X 2 IDT723614 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB can be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted

Contextual Info: HM621664H/HM621864H Series — — Preliminary 65536-word x 16/18-bit High Speed CM O S Static RAM T he H M 621664H /H M 621864H is an asyncronous high speed static R A M organized as 64 kw ord x 1 6 /1 8 b it. It r e a liz e h ig h s p e e d a c c e s s tim e

Contextual Info: HM62W1664HB Series 65536-word x 16-bit High Speed CMOS Static RAM HITACHI ADE-203-415 A (Z) Preliminary Rev. 0.1 Jul. 18, 1996 Description The HM62W1664HB is an asynchronous high speed static RAM organized as 64-kword X 16-bit. It realize high speed access time (25/30 ns) with employing 0.8 (Am CMOS process and high speed circuit

Contextual Info: HM621664HB Series 1 M High Speed SRAM 64-kword x 16-bit HITACHI ADE-203-349B(Z) Rev. 2.0 Nov. 1997 Description The HM621664HB is an asynchronous high speed static RAM organized as 64-kword x 16-bit. It realize high speed access time (15/20 ns) with employing 0.8 (Am CMOS process and high speed circuit designing