AN1642 Search Results

AN1642

Abstract: EN55014 viper12a VIPER12A-E Resistor Fuse 4.91 ViPer12A buck 220V ac to 96V dc converter circuit ic viper12a vip*12a 1N4007
Contextual Info: AN1642 Application note VIPower: 5 V buck SMPS with VIPer12A-E Introduction This paper introduces the 5 V output nonisolated SMPS based on STMicroelectronics’ VIPer12A-E in buck configuration. The power supply is operated in the European voltage range i.e. 185 to 265 Vac. It can supply small loads, such as microcontrollers, motors,

AN1642 VIPower 5V buck smps with VIPer12A

Abstract: VIPer12A applications ic viper12a 5v AN1642 VIPer12A ic viper12a 1n4148 zener diode dz1 ZENER DIODE diode zener 185V viper12a application note
Contextual Info: AN1642 - APPLICATION NOTE VIPower: 5V BUCK SMPS WITH VIPer12A F. Cacciotto – F. Gennaro 1. Abstract This paper introduces the 5V output non-isolated SMPS based on VIPer12A, by STMicroelectronics, in Buck configuration. The power supply is operated in European voltage range i.e. 185 to 265Vac. It can supply small loads,

MC10EP016

Abstract: MC100EP016 MC10E016
Contextual Info: MC10EP016, MC100EP016 3.3V / 5V ECL 8−Bit Synchronous Binary Up Counter The MC10/100EP016 is a high−speed synchronous, presettable, cascadeable 8−bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS family. The counter features internal feedback to TC gated by the TCLD

LVEP210

Abstract: MC100 MC100EP210 MC100LVEP210
Contextual Info: MC100LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is

2824 footprint dimension

Abstract: MC10EP89 HEP89 HP89 MC10EP89-D 964 dfn8
Contextual Info: MC10EP89 3.3V / 5V ECL Coaxial Cable Driver Description The MC10EP89 is a differential fanout gate specifically designed to drive coaxial cables. The device is especially useful in digital video broadcasting applications; for this application, since the system is

Contextual Info: MC100EP195B 3.3V ECL Programmable Delay Chip Descriptions The MC100EP195B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and

100EL15

Abstract: transistor el15 MC100EL15 MC10EL15 el15 transistor
Contextual Info: MC10EL15, MC100EL15 5V ECL 1:4 Clock Distribution Chip The MC10EL/100EL15 is a low skew 1:4 clock distribution chip designed explicitly for low skew clock distribution applications. The VBB pin, an internally generated voltage supply, is available to this device

KPT23

Abstract: marking kpt23 MC100EPT23DG EPT23 MC100EPT23 AN1642
Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL/LVDS to LVTTL Translator The MC100EPT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL Positive ECL or LVDS levels are used, only +3.3 V and ground are required. The small outline 8-lead package

LQFP-32

Abstract: MC12439 MPC9239 NBC12349A NBC12439 NBC12439A PLCC-28
Contextual Info: NBC12439, NBC12439A 3.3V/5V Programmable PLL Synthesized Clock Generator 50 MHz to 800 MHz http://onsemi.com The NBC12439 and NBC12439A are general purpose, PLL based synthesized clock sources. The VCO will operate over a frequency range of 400 MHz to 800 MHz. The VCO frequency is sent to the

Contextual Info: MC100LVEL91 3.3 V Triple LVPECL Input to -3.3 V to -5.0 V ECL Output Translator Description The MC100LVEL91 is a triple LVPECL input to ECL output translator. The device receives low voltage differential PECL signals, determined by the VCC supply level, and translates them to differential

VIPER22A EQUIVALENT

Abstract: prepaid energy meter block diagram gsm using prepaid energy meter circuit diagram AN1642 VIPower 5V buck smps with VIPer12A toshiba crt colour tv kit circuit diagram tv crt charger diagram prepaid energy meter using smart card 1500 watt smps schematic SCHEMATIC DIAGRAM REVERSE KWH METER schematic diagram UPS 600 Power structure
Contextual Info: PART 1 MICROS, LINEARS & DISCRETES 3. L6928D Step-down converter 4. L6382Dx 5. VIPer12A & VIPer22A For Lighting 6. SuperFREDMesh Power MOSFETs 7. Power MOSFETs In Linear Operation 8. Low Profile Power MOSFETs In I2SPAK 9. New 200V Power MOSFETs For µcontrolled ballasts

100EL91

Contextual Info: MC100EL91 5 V Triple PECL Input to −5 V ECL Output Translator The MC100EL91 is a triple PECL input to ECL output translator. The device receives standard voltage differential PECL signals, determined by the VCC supply level, and translates them to differential

KVL11

Contextual Info: MC100LVEL11 3.3V ECL 1:2 Differential Fanout Buffer The MC100LVEL11 is a differential 1:2 fanout buffer. The device is functionally similar to the E111 device but with higher performance capabilities. Having within-device skews and output transition times

Contextual Info: MC10E451, MC100E451 5V ECL 6−Bit D Register Differential Data and Clock The MC10E/100E451 contains six D−type flip−flops with single−ended outputs and differential data inputs. The common clock input is also differential. The registers are triggered by a positive

Contextual Info: MC10E151, MC100E151 5V ECL 6-Bit D Register The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 or both go HIGH. The asynchronous

Contextual Info: MC100LVEL14 3.3V ECL 1:5 Clock Distribution Chip The MC100LVEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is

MC1648 spice model

Abstract: KEL1648 K1648 varactor diode q factor measurement MC100EL1648 application note capacitor 1.3 mF symbol of varactor diode and equivalent circuit
Contextual Info: MC100EL1648 5 V ECL Voltage Controlled Oscillator Amplifier The MC100EL1648 is a voltage controlled oscillator amplifier that requires an external parallel tank circuit consisting of the inductor L and capacitor (C). A varactor diode may be incorporated into the tank

Contextual Info: MC100LVEL30 3.3V ECL Triple D Flip−Flop with Set and Reset The MC100LVEL30 is a triple master−slave D flip−flop with differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the

Contextual Info: MC10H211 Dual 3−Input 3−Output NOR Gate The MC10H211 is designed to drive up to six transmission lines simultaneously. The multiple outputs of this device also allow the wire ORing of several levels of gating for minimization of gate and package count.

kel33

Abstract: HEL33 kl-33 CIRCUIT DIAGRAM FOR IC 810 hl33
Contextual Info: MC10EL33, MC100EL33 5V ECL ÷4 Divider The MC10EL/100EL33 is an integrated ÷4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions,

100LVEL56

Contextual Info: MC100LVEL56 3.3V ECL Dual Differential 2:1 Multiplexer The MC100LVEL56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. The device features both individual and common select inputs to

Contextual Info: MC10EL34, MC100EL34 5V ECL ÷2, ÷4, ÷8 Clock Generation Chip The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common

EL38

Abstract: MC100EL38
Contextual Info: MC100EL38 5V ECL ÷2, ÷4/6 Clock Generation Chip The MC100EL38 is a low skew ÷2, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by

E131

Abstract: MC100EP131 MC10EP131 QFN32 QFN32* socket
Contextual Info: MC10EP131, MC100EP131 3.3V / 5V ECL Quad D Flip−Flop with Set, Reset, and Differential Clock Description The MC10/100EP131 is a Quad Master−slaved D flip−flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables.