AS7C25512NTD32A Search Results

Contextual Info: March 2004 AS7C25512NTD32A AS7C25512NTD36A 2.5V 512K x 32/36 SRAM with NTDTM Features • • • • • • Organization: 524,288 words × 32 or 36 bits NTD 1 architecture for efficient bus operation Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3.5/3.8 ns

Contextual Info: April 2004 AS7C25512NTD32A AS7C25512NTD36A 2.5V 512K x 32/36 SRAM with NTDTM Features • • • • • • Organization: 524,288 words × 32 or 36 bits NTD 1 architecture for efficient bus operation Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3.5/3.8 ns

Contextual Info: March 2004 AS7C251MPFD18A 2.5V 1M x 18 pipelined burst synchronous SRAM Features • Multiple chip enables for easy expansion • 2.5V core power supply • NTD 1 pipelined architecture available AS7C251MNTD18A, AS7C25512NTD32A/ AS7C25512NTD36A • Boundary scan using IEEE 1149.1 JTAG function

AS7C25512NTD32A

Abstract: AS7C25512NTD36A
Contextual Info: December 2002 Advance Information AS7C25512NTD32A AS7C25512NTD36A Š 9 . î  65$0 ZLWK 17'TM Features • Organization: 524,288 words x 32 or 36 bits • NTD 1 architecture for efficient bus operation • Fast clock speeds to 250 MHz in LVTTL/LVCMOS

FDSD

Contextual Info: September 2002 Advance Information AS7C25512NTD32A AS7C25512NTD36A Š 9 . î  65$0 ZLWK 17'TM Features • Organization: 524,288 words x 32 or 36 bits • NTD 1 architecture for efficient bus operation • Fast clock speeds to 250 MHz in LVTTL/LVCMOS

Contextual Info: March 2004 AS7C251MPFS18A 2.5V 1M x 18 pipelined burst synchronous SRAM Features • Multiple chip enables for easy expansion • 2.5V core power supply • NTD 1 pipelined architecture available AS7C251MNTD18A, AS7C25512NTD32A/ AS7C25512NTD36A • Boundary scan using IEEE 1149.1 JTAG function

AS7C251MPFD18A

Abstract: AS7C251MPFS18A AS7C25512NTD32A AS7C25512NTD36A AS7C25512PFS36A
Contextual Info: December 2004 AS7C25512NTD32A AS7C25512NTD36A 2.5V 512K x 32/36 Pipelined SRAM with NTDTM • • • • • • • Features • • • • • • • • Organization: 524,288 words × 32 or 36 bits NTD architecture for efficient bus operation Fast clock speeds to 166 MHz

Contextual Info: December 2002 Advance Information AS7C25512PFS32A AS7C25512PFS36A 2.5V 512K x 32/36 pipelined burst synchronous SRAM Features • • • • • • • • • • • • • • • • • Organization: 524,288 words × 32 or 36 bits Fast clock speeds to 250MHz in LVTTL/LVCMOS

Contextual Info: April 2004 AS7C25512FT32A AS7C25512FT36A 2.5V 512K x 32/36 flowthrough burst synchronous SRAM Features • • • • • • • • • • • • Common data inputs and data outputs • Boundary scan using IEEE 1149.1 JTAG function • NTD 1 flow-through mode architecture available

AS7C251MNTD18A

Abstract: AS7C251MPFD18A AS7C251MPFS18A AS7C25512PFD36A AS7C25512PFS36A
Contextual Info: December 2004 AS7C251MNTD18A 2.5V 1M x 18 Pipelined SRAM with NTDTM Features • • • • • • • • • Organization: 1,048,576 words x 18 bits NTD architecture for efficient bus operation Fast clock speeds to 166 MHz Fast clock to data access: 3.5/3.8 ns

AS7C251MPFD18A

Abstract: AS7C251MPFS18A AS7C25512PFS36A
Contextual Info: April 2005 AS7C25512NTF32A AS7C25512NTF36A 2.5V 512K x 32/36 Flowthrough Synchronous SRAM with NTDTM Features • • • • • • • • • • • • • • • Organization: 524,288 words × 32 or 36 bits NTD architecture for efficient bus operation

Contextual Info: September 2002 Advance Information AS7C251MPFS18A 2.5V 1M x 18 pipelined burst synchronous SRAM Features • • • • • • • • • • • • • Organization: 1,048,576 x18 bits Fast clock speeds to 250MHz in LVTTL/LVCMOS Fast clock to data access: 2.6/2.8/3/3.4 ns

Contextual Info: December 2002 Advance Information AS7C251MPFS18A 2.5V 1M x 18 pipelined burst synchronous SRAM Features • • • • • • • • • • • • • Organization: 1,048,576 x18 bits Fast clock speeds to 250MHz in LVTTL/LVCMOS Fast clock to data access: 2.6/2.8/3/3.4 ns

Contextual Info: March 2004 AS7C25512PFS32A AS7C25512PFS36A 2.5V 512K x 32/36 pipelined burst synchronous SRAM Features • • • • • • • • • • • • • • Organization: 524,288 words × 32 or 36 bits Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3.5/3.8 ns

AS7C251MPFD18A

Abstract: AS7C251MPFS18A AS7C25512PFD36A AS7C25512PFS36A
Contextual Info: December 2004 AS7C25512PFS32A AS7C25512PFS36A 2.5V 512K x 32/36 pipelined burst synchronous SRAM Features • • • • • • • • • Organization: 524,288 words × 32 or 36 bits Fast clock speeds to 166 MHz Fast clock to data access: 3.5/3.8 ns

AS7C251MPFD18A

Abstract: AS7C251MPFS18A AS7C25512PFD36A AS7C25512PFS36A
Contextual Info: December 2004 AS7C251MNTF18A 2.5V 1M x 18 Flowthrough Synchronous SRAM with NTDTM Features • • • • • • • • • • • • • • • Organization: 1,048,576 words x 18 bits NTD architecture for efficient bus operation Fast clock to data access: 7.5/8.5/10 ns

2Y11

Abstract: AS7C251MFT18A AS7C251MPFD18A AS7C251MPFS18A AS7C25512PFD36A AS7C25512PFS36A
Contextual Info: February 2005 AS7C251MPFD18A 2.5V 1M x 18 pipelined burst synchronous SRAM Features • • • • • • • • Organization: 1,048,576 x18 bits Fast clock speeds to 166 MHz Fast clock to data access: 3.5/3.8 ns Fast OE access time: 3.5/3.8 ns Fully synchronous register-to-register operation

AS7C251MFT18A

Abstract: AS7C251MPFD18A AS7C251MPFS18A AS7C25512PFD36A AS7C25512PFS36A
Contextual Info: December 2004 AS7C251MPFS18A 2.5V 1M x 18 pipelined burst synchronous SRAM Features • • • • • • • • Organization: 1,048,576 x18 bits Fast clock speeds to 166 MHz Fast clock to data access: 3.5/3.8 ns Fast OE access time: 3.5/3.8 ns Fully synchronous register-to-register operation

Contextual Info: November 2005 AS7C25512NTF32A AS7C25512NTF36A 2.5V 512K x 32/36 Flowthrough Synchronous SRAM with NTDTM Features • • • • • • • • • • • • • • • Organization: 524,288 words × 32 or 36 bits NTD architecture for efficient bus operation

10AS7C251MFT18A-85TQC

Abstract: AS7C251MFT18A AS7C251MFT18A-85BC AS7C251MFT18A-85TQI AS7C251MNTD18A AS7C25512NTD32A AS7C25512NTD36A CE01 F 1310
Contextual Info: April 2004 AS7C251MFT18A 2.5V 1M x 18 flowthrough burst synchronous SRAM Features • • • • • • • • • • • • • Organization: 1,048,576 words x18 bits Fast clock to data access: 8.5/10 ns Fast OE access time: 3.5/3.8 ns Fully synchronous flow-through operation

AS7C25512NTD32A

Abstract: AS7C25512NTD36A AS7C25512PFD36A AS7C25512PFS36A
Contextual Info: October 2001 Advanced Information AS7C25512PFD32A AS7C25512PFD36A 2.5V 512K x 32/36 pipeline burst synchronous SRAM Features • 100-pin TQFP package • 119-Ball BGA 7 x 17 Ball Grid Array Package • Byte write enables • Multiple chip enables for easy expansion

Contextual Info: November 2005 AS7C251MNTF18A 2.5V 1M x 18 Flowthrough Synchronous SRAM with NTDTM Features • • • • • • • • • • • • • • • Organization: 1,048,576 words x 18 bits NTD architecture for efficient bus operation Fast clock to data access: 7.5/8.5/10 ns

Contextual Info: March 2004 AS7C25512PFD32A AS7C25512PFD36A 2.5V 512K x 32/36 pipelined burst synchronous SRAM Features • • • • • • • • • • • • • • • • Organization: 524,288 words × 32 or 36 bits Fast clock speeds to 166 MHz in LVTTL/LVCMOS

T T 2190

Contextual Info: September 2002 Advance Information AS7C25512PFS32A AS7C25512PFS36A 2.5V 512K x 32/36 pipelined burst synchronous SRAM Features • • • • • • • • • • • • • • • • • Organization: 524,288 words × 32 or 36 bits Fast clock speeds to 250MHz in LVTTL/LVCMOS