CD54AC109 Search Results

AC109

Abstract: CD54AC109 CD54AC109F3A CD74AC109 CD74AC109E CD74AC109M96
Contextual Info: CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 D D D D D D CD54AC109 . . . F PACKAGE CD74AC109 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

IC 544-S

Contextual Info: L 4302271 0Q2bl70 b H i HAS 37E _ HARRIS semicond sector High-Reliability Advanced CMOS Logic ICs '-“F U k '0 7 -0 7 Recent Additions CD54AC109/3A CD54ACT109/3A SW IT C H IN G C H A R A C T E R IS T IC S : A C Series; tr, t, = 3 ns, C L = 50 pF Worst Case

Contextual Info: CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 D D D D D D CD54AC109 . . . F PACKAGE CD74AC109 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

Contextual Info: CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 D D D D D D CD54AC109 . . . F PACKAGE CD74AC109 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

AC109

Abstract: CD54AC109 CD54AC109F3A CD74AC109 CD74AC109E CD74AC109M96
Contextual Info: CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 D D D D D D CD54AC109 . . . F PACKAGE CD74AC109 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

Contextual Info: CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 D D D D D D CD54AC109 . . . F PACKAGE CD74AC109 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

AC109

Abstract: CD54AC109 CD54AC109F3A CD74AC109 CD74AC109E CD74AC109M96
Contextual Info: CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 D D D D D D CD54AC109 . . . F PACKAGE CD74AC109 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

Contextual Info: CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 D D D D D D CD54AC109 . . . F PACKAGE CD74AC109 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

Contextual Info: 17E High-Reliability Advanced CMOS Logic IC s_ Recent Additions CD54AC109/3A CD54ACT109/3A D • 3075001 0024=177 0 G E S0LI1 STATE —i— i n 1 T 4b-ö7 •O / Dual “J-K” Flip-Flop with Set and Reset Positlve-Edge-Triggered J, K) The RCA CD54AC109 and CD54ACT109 are dual “J-K” flipflops with set and reset that utilize the new RCA ADVANCED

Contextual Info: High-Reliability Advanced CMOS Logic ICs Recent Additions CD54AC109/3A CD54ACT109/3A SWITCHING CHARACTERISTICS: AC Series; t„ t, = 3 ns, CL = 50 pF Worst Case CHARACTERISTICS SYMBOL Propagation Delays: CP (CP) to Q, Q Vcc (V) 1.5 3.3* S, R to Q, Q tpHL

Contextual Info: High-Reliability Advanced CMOS Logic ICs Recent Additions CD54AC109/3A CD54ACT109/3A Dual “J-K” Flip-Flop with Set and Reset Positive-Edge-Triggered J, K The RCA CD54AC109 and CD54ACT109 are dual “J-K ” flipflops w ith set and reset that utilize the new RCA ADVANCED

CD54AC112

Abstract: CD54ACT112
Contextual Info: High-Reliability Advanced CMOS Logic ICs Recent Additions CD54AC109/3A CD54ACT109/3A SWITCHING CHARACTERISTICS: AC Series; tr, t, = 3 ns, CL = 50 pF Worst Case SYMBOL CHARACTERISTICS Propagation Delays: CP (CP) to Q, U tp L H tp H L S, R to Q, Q tp H L Power Dissipation Capacitance

AC109

Abstract: CD54AC109 CD54AC109F3A CD74AC109 CD74AC109E CD74AC109M96
Contextual Info: CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 D D D D D D CD54AC109 . . . F PACKAGE CD74AC109 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

Contextual Info: CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 D D D D D D CD54AC109 . . . F PACKAGE CD74AC109 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

CD54AC109

Abstract: CD54AC112 CD54ACT109
Contextual Info: High-Reliability Advanced C M O S Logic ICs Recent Additions CD54AC109/3A CD54ACT109/3A Dual “J-K” Flip-Flop with Set and Reset Positive-Edge-Triggered J, K T h e R C A C D 54A C 109 and C D 54A C T 109 are dua l “ J -K ” flip ­ flo p s w ith set and reset th a t u tilize th e new R CA A D V A N C E D

AC109

Abstract: CD54AC109 CD54AC109F3A CD74AC109 CD74AC109E CD74AC109M96
Contextual Info: CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 D D D D D D CD54AC109 . . . F PACKAGE CD74AC109 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

Contextual Info: CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 D D D D D D CD54AC109 . . . F PACKAGE CD74AC109 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

Contextual Info: CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 D D D D D D CD54AC109 . . . F PACKAGE CD74AC109 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

Contextual Info: CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 D D D D D D CD54AC109 . . . F PACKAGE CD74AC109 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

Contextual Info: CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 D D D D D D CD54AC109 . . . F PACKAGE CD74AC109 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

Contextual Info: CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 D D D D D D CD54AC109 . . . F PACKAGE CD74AC109 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

AC109

Abstract: CD54AC109 CD54AC109F3A CD74AC109 CD74AC109E CD74AC109M96
Contextual Info: CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 D D D D D D CD54AC109 . . . F PACKAGE CD74AC109 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

JM38510

Abstract: JM38510/05202BCA 54FCT540DMQB 54ACT00DMQB Mil JAN jm38510 Cross Reference national semiconductor cmos JM38510/05302 54ACT374DMQB JM38510-05003BCA 7704601CA
Contextual Info: Harris Semiconductor to National Semiconductor CMOS DIGITAL CROSS-REFERENCE GUIDE REV. 12/98 Harris Part # CD54AC00F3A CD54AC02F3A CD54AC04F3A CD54AC05F3A CD54AC08F3A CD54AC109F3A CD54AC138F3A CD54AC139F3A CD54AC153F3A CD54AC157F3A CD54AC161F3A CD54AC163F3A

CD54AC109

Abstract: CD54AC112 CD54ACT109 CD54ACT112
Contextual Info: Hlgh-Rellablllly Advanced CMOS Logic IC s - E Z 5 - ^ _1 4 3 0 5 5 7 1 Recent Additions CD54AC109/3A CD54ACT109/3A QQgblbq T HHAS HARRIS SEI1IC0NI SECT0R —i— ' ¿ i t c f i " P ^ -0 -7 -0 7 Dual “J-K” Flip-Flop with Set and Reset Positive-Edge-Triggered J, K)