CDC509 Search Results

Contextual Info: CDC509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS576C − JULY 1996 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D NOT RECOMMENDED FOR NEW DESIGNS this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications

Contextual Info: CDC509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER _ SCAS576B -JU LY 1996-REVISED JANUARY 1996 PW PACKAGE TOP VIEW Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs

CDC509

Abstract: CDC509PWR CDC509PWRG4 CDCVF2509A MTSS001C
Contextual Info: CDC509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS576C − JULY 1996 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D NOT RECOMMENDED FOR NEW DESIGNS this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications

Contextual Info: CDC509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS576C − JULY 1996 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D NOT RECOMMENDED FOR NEW DESIGNS this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications

Contextual Info: CDC509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS576C − JULY 1996 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D NOT RECOMMENDED FOR NEW DESIGNS this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications

Contextual Info: CDC509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _ SCASS76A - JULY 1996 - REVISED OCTOBER 1896 Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs

Contextual Info: CDC509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS576C − JULY 1996 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D NOT RECOMMENDED FOR NEW DESIGNS this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications

CDC509

Abstract: CDC509PWR CDC509PWRG4 CDCVF2509A MTSS001C
Contextual Info: CDC509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS576C − JULY 1996 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D NOT RECOMMENDED FOR NEW DESIGNS this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications

Contextual Info: CDC509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS576C − JULY 1996 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D NOT RECOMMENDED FOR NEW DESIGNS this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications

Contextual Info: CDC509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS576C − JULY 1996 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D NOT RECOMMENDED FOR NEW DESIGNS this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications

Contextual Info: CDC509PWR IL08 PHASE LOCK LOOP CLOCK DRIVER —TOP VIEW— AGND 1 24 CLK IN VCC 2 23 AVCC 1Y0 OUT 3 22 VCC 1Y1 OUT 4 21 2Y0 OUT 1Y2 OUT 5 20 2Y1 OUT GND 6 19 GND GND 7 18 GND 1Y3 OUT 8 17 2Y2 OUT 1Y4 OUT 9 16 2Y3 OUT VCC 10 15 VCC 1G IN 11 14 2G IN FBOUT OUT 12

Contextual Info: CDC509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _ SCASS76A - JULY 1998 - REVISED OCTOBER 1996 Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs

Contextual Info: CDC509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS576C − JULY 1996 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D NOT RECOMMENDED FOR NEW DESIGNS this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications

CDC509

Abstract: CDC509PWR
Contextual Info: CDC509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS576B – JULY 1996 – REVISED JANUARY 1998 D D D D D D D PW PACKAGE TOP VIEW Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs

CDC509

Contextual Info: CDC509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS576A – JULY 1996 – REVISED OCTOBER 1996 D D D D D D PW PACKAGE TOP VIEW Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of

Contextual Info: CDC509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS576C − JULY 1996 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D NOT RECOMMENDED FOR NEW DESIGNS this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications

CDC509

Contextual Info: CDC509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS576A - JULY 1996 - REVISED OCTOBER 1996 Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output

CDC509

Abstract: CDC509PWR
Contextual Info: CDC509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS576B – JULY 1996 – REVISED JANUARY 1998 D D D D D D D PW PACKAGE TOP VIEW Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs

PC133 registered reference design

Contextual Info: CDCF2509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS624C − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

Contextual Info: CDCVF2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS637B – DECEMBER 1999 – REVISED JULY 2001 D D D D D D D D D D D D D D PW PACKAGE TOP VIEW Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1 Spread Spectrum Clock Compatible

CDC2510A

Contextual Info: CDC2510C 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS621A − DECEMBER 1998 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC SDRAM Registered DIMM Design Support Document Rev. 1.2

CDC2510A

Contextual Info: CDC2510C 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS621A − DECEMBER 1998 − REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC SDRAM Registered DIMM Design Support Document Rev. 1.2

PC133 registered reference design

Contextual Info: CDCVF2509A www.ti.com SCAS765A – APRIL 2004 – REVISED JULY 2004 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE FEATURES FEATURES • • • • • • • • • • • • • • • • • • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification

CDC2510B

Abstract: CDC2510BPWR Y3020
Contextual Info: CDC2510B 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS612 – SEPTEMBER 1998 D D D D D D D D D D D D D D PW PACKAGE TOP VIEW Designed to Meet PC SDRAM Registered DIMM Specification Spread Spectrum Clock Compatible Operating Frequency 25 MHz to 125 MHz tPhase Error Minus Jitter at 66MHz to