CY23FP12OCT Search Results

CY23FP12OCT Datasheets (2)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF	PDF Size	Page count
CY23FP12OCT		Cypress Semiconductor	Logic ICS, 200MHz Field Programmable Zero Delay Buffer, Tape and Reel		Original	PDF	89.51KB	10
CY23FP12OCT		Cypress Semiconductor			Original	PDF	203.83KB	10

CY23FP12OCT Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
CY23FP12 Contextual Info: CY23FP12 200 MHz Field Programmable Zero Delay Buffer Functional Description Features • Fully field-programmable ❐ Input and output dividers ❐ Inverting/noninverting outputs ❐ Phase-locked loop PLL or fanout buffer configuration ■ 10 MHz to 200 MHz operating range	Original	CY23FP12 28-pin CY23FP12	PDF
CY23FP12 Abstract: CY23FP12OC CY3672 Contextual Info: CY23FP12 200-MHz Field Programmable Zero Delay Buffer Features Functional Description • Fully field-programmable: — Input and output dividers — Inverting/noninverting outputs • • • • • • • • • • • • • — Phase-locked loop PLL or fanout buffer configuration	Original	CY23FP12 200-MHz 10-MHz 28-pin CY23FP12 CY23FP12OC CY3672	PDF
CY23FP12 Contextual Info: CY23FP12 200 MHz Field Programmable Zero Delay Buffer 200 MHz Field Programmable Zero Delay Buffer Features Functional Description • Fully field-programmable ❐ Input and output dividers ❐ Inverting/non-inverting outputs ❐ Phase-locked loop PLL or fanout buffer configuration	Original	CY23FP12 28-pin CY23FP1imited CY23FP12	PDF
CY23FP12 Abstract: CY23FP12OC CY3672 PS11011 Contextual Info: CY23FP12 200-MHz Field Programmable Zero Delay Buffer Features Functional Description • Fully field-programmable — Input and output dividers — Inverting/noninverting outputs — Phase-locked loop PLL or fanout buffer configuration • 10-MHz to 200-MHz operating range	Original	CY23FP12 200-MHz 10-MHz 28-pin CY23FP12 CY23FP12OC CY3672 PS11011	PDF
CY23FP12 Abstract: CY23FP12OC CY3672 Contextual Info: CY23FP12 200-MHz Field Programmable Zero Delay Buffer Features Functional Description • Fully field-programmable — Input and output dividers — Inverting/noninverting outputs • • • • • • • • • • • • • — Phase-locked loop PLL or fanout buffer configuration	Original	CY23FP12 200-MHz 10-MHz 28-pin CY23FP12 CY23FP12OC CY3672	PDF
CY23FP12 Abstract: CY23FP12OXC CY3692 Contextual Info: CY23FP12 200 MHz Field Programmable Zero Delay Buffer Features Functional Description • Fully field-programmable ❐ Input and output dividers ❐ Inverting/noninverting outputs ❐ Phase-locked loop PLL or fanout buffer configuration ■ 10 MHz to 200 MHz operating range	Original	CY23FP12 CY23FP12 CY23FP12OXC CY3692	PDF
CY23FP12 Abstract: CY23FP12OC CY3672 Contextual Info: CY23FP12 200-MHz Field Programmable Zero Delay Buffer Features Functional Description • Fully field-programmable — Input and output dividers — Inverting/noninverting outputs — Phase-locked loop PLL or fanout buffer configuration • 10-MHz to 200-MHz operating range	Original	CY23FP12 200-MHz 10-MHz 28-pin CY23FP12 CY23FP12OC CY3672	PDF
CY23FP12 Abstract: CY23FP12OC CY3672 Contextual Info: CY23FP12 200-MHz Field Programmable Zero Delay Buffer Features Functional Description • Fully field-programmable: — Input and output dividers — Inverting/noninverting outputs • • • • • • • • • • • • • — Phase-locked loop PLL or fanout buffer configuration	Original	CY23FP12 200-MHz 10-MHz 28-pin CY23FP12 CY23FP12OC CY3672	PDF
CY23FP12 Abstract: CY23FP12OXC CY3692 ADP006 Contextual Info: CY23FP12 200 MHz Field Programmable Zero Delay Buffer Features Functional Description • Fully Field-Programmable ❐ Input and output dividers ❐ Inverting/noninverting outputs ❐ Phase-locked loop PLL or fanout buffer configuration ■ 10 MHz to 200 MHz Operating Range	Original	CY23FP12 28-pin CY23FP12 CY23FP12OXC CY3692 ADP006	PDF