CY7C371 Search Results

Contextual Info: CY7C371i UltraLogic 32-Macrocell Flash CPLD Features signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. • • • • 32 macrocells in two logic blocks 32 I/O pins

7C371-110

Abstract: 7C371-143 7C371-83 CY7C371 CY7C372 FLASH370
Contextual Info: For new designs see CY7C371i CY7C371 UltraLogic 32-Macrocell Flash CPLD Features • • • • • • of use and high performance of the 22V10 to high-density CPLDs. 32 macrocells in two logic blocks 32 I/O pins 6 dedicated inputs including 2 clock pins

Contextual Info: 32-Macrocell Flash CPLD Features Functional Description • 32 macrocells in two logic blocks The CY7C371 is a Flash erasable Complex Programmable Logic Device CPLD and is part of the F lash370 ” family of highdensity, high-speed CPLDs. Like all mem­

u2330

Contextual Info: fax id: 6126 CY7C371 p ro : V « *1 X X - UltraLogic 32-Macrocell Flash CPLD F lash 370 family, the CY7C371 is designed to bring the ease of use and high performance of the 22V10 to high-density CPLDs. Feat ures • 32 m acrocells in two logic blocks The 32 macrocells in the CY7C371 are divided between two

l83A

Contextual Info: fax id: 6126 CY7C371 CYPRESS UltraLogic 32-Macrocell Flash CPLD FLASH370 fam ily the CY7C371 is designed to bring the ease of use and high performance of the 22V10 to high-density CPLDs. Features • 32 macrocells in two logic blocks • 32 I/O pins The 32 macrocells in the CY7C371 are divided between two

vhdl code cy7b933

Abstract: free vhdl code download for pll architecture of cypress FLASH370 cpld CY7B933 CY7B923 CY7C371 CY7C371-66 FLASH370 NOR flash controller vhdl code vhdl code for fifo
Contextual Info: fax id: 6416 Implementing a Reframe Controller for the CY7B933 HOTLink Receiver in a CY7C371 CPLD Introduction This application note describes a reframe controller for the Cypress CY7B933 HOTLink Receiver. The primary function of the controller is to monitor the Receive Violation Symbol

7C371-143

Abstract: 7C371-83 7C371L-83 CY7C371 CY7C372 FLASH370 7C371-110
Contextual Info: 7c371: Tuesday, May 26, 1992 Revision: August 9, 1995 CY7C371 UltraLogict 32ĆMacrocell Flash CPLD Features Functional Description D D D The CY7C371 is a Flash erasable Complex Programmable Logic Device CPLD and is part of the FLASH370 family of highĆdenĆ

architecture of cypress FLASH370 cpld

Abstract: 7C371-110 FLASH370 architecture of cypress FLASH370 device 7C371-143 7C371-83 7C371L-83 CY7C371 CY7C372 architecture of cypress FLASH370
Contextual Info: fax id: 6126 1CY 7C37 1 For new designs, see CY7C371i. CY7C371 UltraLogic 32-Macrocell Flash CPLD Features • • • • • of use and high performance of the 22V10 to high-density CPLDs. 32 macrocells in two logic blocks 32 I/O pins 6 dedicated inputs including 2 clock pins

3.3v to 5v buffer latch

Abstract: preset resistor 3.3v to 5v interface components
Contextual Info: fax id: 6136 PRELIMINARY CY7C371i UltraLogic 32-Macrocell Flash CPLD Features signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. • • • • 32 macrocells in two logic blocks

cypress FLASH370

Abstract: 7C371-110 7C371-143 7C371-83 CY7C371 CY7C372 FLASH370
Contextual Info: CY7C371 UltraLogic 32-Macrocell Flash CPLD Features • • • • • • of use and high performance of the 22V10 to high-density CPLDs. 32 macrocells in two logic blocks 32 I/O pins 6 dedicated inputs including 2 clock pins Bus Hold capabilities on all I/Os and dedicated inputs

Contextual Info: 71i CY7C371i UltraLogic 32-Macrocell Flash CPLD Features signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. • • • • 32 macrocells in two logic blocks 32 I/O pins

vhdl code for 4 bit updown counter

Abstract: 4 bit updown counter vhdl code vhdl code for asynchronous fifo fifo vhdl vhdl code for a updown counter 4 bit gray code counter VHDL cypress FLASH370 C371 CY7C371 FLASH370
Contextual Info: FIFO Dipstick Using Warp2 VHDL and the CY7C371 Introduction Programmable FIFO flags can often simplify the design of a digital system by automatically indicating a status that can prevent overrun or underrun in an elastic FIFO buffer. Although many FIFOs are available with on-chip programmable

Contextual Info: fax id: 6136 PRELIMINARY CY7C371 i UltraLogic 32-Macrocell Flash CPLD Features sig ne d to bring the ease of use and high pe rfo rm an ce o f the 22V 10, as w ell as PCI Local Bus S pe cifica tion sup po rt, to high -den sity CPLDs. • 32 m a cro c ells in tw o logic blocks

Contextual Info: fax id: 6136 CY7C371 i ^C YPR ESS UltraLogic 32-Macrocell Flash CPLD Features sig ne d to bring the ease of use and high pe rfo rm an ce o f the 22V 10, as w ell as PCI Local Bus S pe cifica tion sup po rt, to high -den sity CPLDs. • 32 m a cro c ells in tw o logic blocks

tunel

Abstract: 140C JESD22
Contextual Info: Cypress Semiconductor Qualification Report QTP# 98116 VERSION 1.0 April, 1998 UltraLogic 32-Macrocell Flash CPLD CY7C371i Cypress Semiconductor UltraLogic 32-Mcell Flash CPLD Device: CY7C371i Package: 44-pin PLCC QTP# 98116 Version 1.0 Page 2 of 8 April, 1988

Contextual Info: fax id: 6136 1CY 7C37 1i PRELIMINARY CY7C371i UltraLogic 32-Macrocell Flash CPLD Features signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. • • • • 32 macrocells in two logic blocks

ic0116

Contextual Info: CY7C371 CYPRESS UltraLogic 32-Macrocell Flash CPLD Features F unctional D escrip tion • 32 m acrocells in two logic blocks • 32 I/O pins • 6 d ed icated in p u ts in clu d in g 2 clock p in s • N o h id d en d elays T h e C Y 7C 371 is a F la sh e ra s a b le C o m p lex

Contextual Info: fax id: 6136 CY7C371 i ^C YPR ESS UltraLogic 32-Macrocell Flash CPLD Features sig ne d to bring the ease of use and high pe rfo rm an ce o f the 22V 10, as w ell as PCI Local Bus S pe cifica tion sup po rt, to high -den sity CPLDs. • 32 m a cro c ells in tw o logic blocks

Contextual Info: V CYPRESS CY7C371 UltraLogic 32-Macrocell Flash CPLD Features Functional Description • 32 macrocells in two logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • No hidden delays • High speed — Ímax = 143 MHz The CY7C371 is a Flash erasable Complex

ULTRA37000

Contextual Info: USE ULTRA37000 FOR ALL NEW DESIGNS CY7C371i UltraLogic™ 32-Macrocell Flash CPLD Features • • • • • • • • • • • designed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to

architecture of cypress FLASH370 cpld

Abstract: 7C371-110 7C371-143 CY7C371 CY7C372 FLASH370
Contextual Info: fax id: 6126 For new designs see CY7C371i CY7C371 UltraLogic 32-Macrocell Flash CPLD Features • • • • • • of use and high performance of the 22V10 to high-density CPLDs. 32 macrocells in two logic blocks 32 I/O pins 6 dedicated inputs including 2 clock pins

cypress flash 370 device

Abstract: cypress flash 370 CPLD features cypress flash 370 cypress flash 370 logic block diagram of cypress flash 370 device cypress flash 370 technology cypress flash 370 device technology
Contextual Info: fax id: 6126 For new designs, see CY7C371L CY7C371 UltraLogic 32-Macrocell Flash CPLD of use and high performance of the 22V10 to high-density CPLDs. Featu res • 32 macrocells in two logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins

asynchronous fifo vhdl

Abstract: ELRAD 8 bit updown counter vhdl CY7C371 FLASH370
Contextual Info: Cypress OnLine Vol 2/#2 11/12/96 11:14 AM Page 7 1,1 U LT R A L O G I C S O L U T I O N S Build a FIFO “Dipstick” With a CY7C371 CPLD Programmable FIFO flags can simplify the design of a digital system. They do it by automatically indicating a status

ULTRA37000

Contextual Info: USE ULTRA37000 FOR ALL NEW DESIGNS CY7C371i UltraLogic™ 32-Macrocell Flash CPLD Features • • • • • • • • • • • designed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to