DS1100 Search Results

74F04

Abstract: 74LS DS1100 DS1100L DS1100LU DS1100LZ J-STD-020A
Contextual Info: PRELIMINARY DS1100L 3.3-Volt 5-Tap Economy Timing Element Delay Line www.maxim-ic.com FEATURES § § § § § § § § § § § PIN ASSIGNMENT All-silicon timing circuit 5-taps equally spaced Delays are stable and precise Both leading and trailing edge accuracy

free circuit diagram for voltage controlled oscillator

Abstract: DS1065 Car security system block diagram DS1000 DS1023 DS1073 DS1077 DS1085 DS1086 DS1100
Contextual Info: Maxim > App Notes > OSCILLATORS/DELAY LINES/TIMERS/COUNTERS SIGNAL GENERATION CIRCUITS Keywords: delay lines, cmos delay line, DS1100, DS1135, DS1065, DS1110, DS1073 Aug 30, 2002 APPLICATION NOTE 209 How Delay Lines Work Abstract: This application brief describes the techniques used to build and calibrate/compensate newgeneration all-silicon delay lines. Both EconOscillators and delay lines use a compensated voltage-controlled

Contextual Info: 19-5736; Rev 10/11 DS1100L 3.3V 5-Tap Economy Timing Element Delay Line GENERAL DESCRIPTION FEATURES The DS1100L is a 3.3V version of the DS1100. It is characterized for operation over the range 3.0V to 3.6V. The DS1100L series delay lines have five equally spaced taps providing delays from

74LS04 Hex Inverter definition

Abstract: 74ls04 dip ttl cmos advantages disadvantages 74LS04 DS-1100 Appnote14 TTL 74ls04 data DS1005 DS1100 DS1110
Contextual Info: Maxim > App Notes > Oscillators/Delay Lines/Timers/Counters Keywords: DS1100, DS1135, DS1110, delay line, hybrid delay line, digital delay line, FAQ Sep 30, 2002 APPLICATION NOTE 14 Design Considerations for All-Silicon Delay Lines Abstract: This application brief discusses the architectural and structural differences between solid-state and

74F04

Abstract: 74LS DS1000 DS1100 DS1100U-xxx DS1100-XXX
Contextual Info: 19-5735; Rev 3/11 DS1100 5-Tap Economy Timing Element Delay Line GENERAL DESCRIPTION FEATURES The DS1100 series delay lines have five equally spaced taps providing delays from 4ns to 500ns. These devices are offered in surface-mount packages to save PCB area. Low cost and

DS1100

Abstract: burn-in
Contextual Info: DALLAS SEMICONDUCTOR 4401 South Beltwood Parkway Dallas, Texas 75244-3292 972 371-4000 Date: July 31, 2000 Subject: PRODUCT CHANGE NOTICE – G003102 Description: DS1100 Burn-in Elimination.

74F04

Abstract: 74LS DS1100 DS1100L J-STD-020A
Contextual Info: Preliminary DS1100L 3-Volt 5-Tap Economy Timing Element Delay Line www.dalsemi.com FEATURES PIN ASSIGNMENT All-silicon timing circuit 5-taps equally spaced Delays are stable and precise Both leading and trailing edge accuracy 3V version of the DS1100 Low-power CMOS

frequency doubler

Abstract: "XOR Gate" DS1100 DS-1100 AN881 APP881 DS1004 DS1035 DS1135 "Frequency doubler"
Contextual Info: Maxim > App Notes > OSCILLATORS/DELAY LINES/TIMERS/COUNTERS Keywords: clock doubler, delay line, frequency doubler, DS1135, DS1100, delay lines, dealy line Dec 12, 2001 APPLICATION NOTE 881 Tech Brief 32: Frequency Doubler using Delay Lines Abstract: Any independent delay line, in conjunction with a XOR gate, can be made into a clock frequency

DS-1100

Contextual Info: 19-5736; Rev 10/11 DS1100L 3.3V 5-Tap Economy Timing Element Delay Line GENERAL DESCRIPTION FEATURES The DS1100L is a 3.3V version of the DS1100. It is characterized for operation over the range 3.0V to 3.6V. The DS1100L series delay lines have five equally spaced taps providing delays from

150MIL

Abstract: 74F04 74LS DS1100 DS1100L DS1100LU DS1100LZ DS1100LZ-250 J-STD-020A
Contextual Info: DS1100L 3.3V 5-Tap Economy Timing Element Delay Line www.maxim-ic.com PIN ASSIGNMENT FEATURES § § § § § All-Silicon Timing Circuit Five Taps Equally Spaced Delays are Stable and Precise Both Leading- and Trailing-Edge Accuracy 3.3V Version of the DS1100

DS1077

Abstract: DS1100 DS-1135 DS1077L DS1085 DS1085L DS1110 DS1135 DS1135L
Contextual Info: Maxim > App Notes > OSCILLATORS/DELAY LINES/TIMERS/COUNTERS Keywords: delay lines, EconOscillator, decoupling, econoscillators, DS1085, DS1077, DS1100, DS1135, DS1135L, DS1110, DS1110LD Sep 10, 2002 APPLICATION NOTE 220 Decoupling Requirements for the DS1077/DS1085 EconOscillators

AN-977

Abstract: AN977 APP977 DS1020 DS1021 DS1023 DS1040 DS1100 DS1110 DS1135
Contextual Info: Maxim > App Notes > OSCILLATORS/DELAY LINES/TIMERS/COUNTERS Keywords: delay lines, one-shot, pulse-width modulator, PWM, DS1100, DS1135, DS1110, DS1020, DS1021, DS1023, DS1123 Feb 22, 2002 APPLICATION NOTE 977 Tech Brief 34: Building Precision Pulse Width Modulators Using

PS1100

Contextual Info: li I g i|# i DS1100 8£ftllCONDUCTOft 5-Tap Economy Timing -, ^ f . ~ Element Delay Line PIN ASSIGNMENT FEATURES All-silicon timing circuit 5-taps equally spaced Delays are stable and precise Both leading and trailing edge accuracy Improved replacement for DS1000

150MIL

Abstract: 74F04 74LS DS1100 DS1100L DS1100LU DS1100LZ J-STD-020A
Contextual Info: PRELIMINARY DS1100L 3.3V 5-Tap Economy Timing Element Delay Line www.maxim-ic.com PIN ASSIGNMENT FEATURES § § § § § § § § § § § All-Silicon Timing Circuit Five Taps Equally Spaced Delays are Stable and Precise Both Leading- and Trailing-Edge Accuracy

ic ttl 74ls

Abstract: 150MIL 74F04 74LS DS1100 DS1100L DS1100LU DS1100LZ DS1100LZ-250 J-STD-020A
Contextual Info: DS1100L 3.3V 5-Tap Economy Timing Element Delay Line www.maxim-ic.com PIN ASSIGNMENT FEATURES § § § § § § § § § § § All-Silicon Timing Circuit Five Taps Equally Spaced Delays are Stable and Precise Both Leading- and Trailing-Edge Accuracy 3.3V Version of the DS1100

DS1100

Abstract: 74F04 74LS DS1000
Contextual Info: DS1100 5-Tap Economy Timing Element Delay Line www.dalsemi.com FEATURES § § § § § § § § § § § PIN ASSIGNMENT All-silicon timing circuit 5-taps equally spaced Delays are stable and precise Both leading and trailing edge accuracy Improved replacement for DS1000

DS1220Y-150 equivalent

Abstract: DS-1100 DS1267S-100 DS1267S-010 DS1233Z-5 DS0621 DS1868 ds17287-5 DS1221SN DS1640
Contextual Info: DS1100 5-Tap Economy Timing Element Delay Line www.dalsemi.com FEATURES § § § § § § § § § § § PIN ASSIGNMENT All-silicon timing circuit 5-taps equally spaced Delays are stable and precise Both leading and trailing edge accuracy Improved replacement for DS1000

Contextual Info: 19-5735; Rev 3/11 DS1100 5-Tap Economy Timing Element Delay Line GENERAL DESCRIPTION FEATURES The DS1100 series delay lines have five equally spaced taps providing delays from 4ns to 500ns. These devices are offered in surface-mount packages to save PCB area. Low cost and

Contextual Info: Embedded Power for Business-Critical Continuity ✁ ✠ ✂ ✄ ✡ ☎ ✞ ✆ ✞ ✄ ☎ ☎ ☎ ✞ DS1100PED 1100 Watts Distributed Power System Front-end Bulk Power Total Output Power: 1100 W continuous Wide Input Voltage: 90 to 264 Vac Electrical Specifications

DS-1135

Abstract: DS1100 programmable delay DS1000 DS1004 DS1005 DS1007 DS1020 DS1033 DS1040
Contextual Info: Maxim > App Notes > COMMUNICATIONS CIRCUITS OSCILLATORS/DELAY LINES/TIMERS/COUNTERS Keywords: delay lines, silicon timed circuits, dealy lines, STCs, DS1040, DS1135L, DS1020, DS1045, DS1033, DS1044, DS1007, DS1000, DS1004, DS1005, DS1100, DS1100L, DS1010, DS1021, DS1013, DS1035,

150MIL

Abstract: 74F04 74LS DS1000 DS1100 J-STD-020A
Contextual Info: DS1100 5-Tap Economy Timing Element Delay Line www.maxim-ic.com PIN ASSIGNMENT FEATURES § § § § § § § § § § § § All-Silicon Timing Circuit Five Taps Equally Spaced 5V Operation Delays are Stable and Precise Both Leading- and Trailing-Edge Accuracy

DS1100Z-250

Abstract: 74F04 74LS DS1000 DS1100 J-STD-020A
Contextual Info: DS1100 5-Tap Economy Timing Element Delay Line www.dalsemi.com FEATURES PIN ASSIGNMENT All-silicon timing circuit 5-taps equally spaced 5V Operation Delays are stable and precise Both leading and trailing edge accuracy Improved replacement for DS1000 Low-power CMOS

AN983

Abstract: Direct Replacement APP983 DS1004 DS1005 DS1013 DS1020 DS1021 DS1023 DS1100
Contextual Info: Maxim > App Notes > OSCILLATORS/DELAY LINES/TIMERS/COUNTERS Keywords: delay line, ST&C, STC, DS1100, DS1135, DS1020, DS1021, DS1023, DS1004, DS1005, DS1013 Feb 28, 2002 APPLICATION NOTE 983 Tech Brief 37: Replacing Passive Hybrid Delay Lines with All-Silicon

"Delay Lines"

Abstract: phase shift DS1100U-20 single phase to 3 phase
Contextual Info: Tech Brief 31 Using Delay Lines to Generate Multi-Phased Clocks www.maxim-ic.com Speeding up Digital Systems With Delay Lines A tapped delay line can produce multiple clock phases very simply. As an example, with a 50MHz input, a DS1100U-20 5ns per tap will produce phase shifts of 90°, 180°, and 270° at the Phase 1, Phase 2, and