DS312 Search Results

11-B

Abstract: DS31256 DS3134 SV54
Contextual Info: DEMO KIT AVAILABLE DS31256 Envoy 256-Channel, High-Throughput HDLC Controller www.maxim-ic.com GENERAL DESCRIPTION The DS31256 Envoy is a 256-channel HDLC controller capable of handling up to 64 T1 or E1 data streams or two T3 data streams. Each of the 16 physical ports can handle one, two, or four

xc3s500e fg320

Abstract: intel strataflash j3d SPARTAN 3E STARTER BOARD transistor tt 2222 pin configuration 500K variable resistor eeprom programmer schematic winbond AT45DB AT49 jtag cable Schematic XC3S500E spartan 3a
Contextual Info: Spartan-3E FPGA Family: Complete Data Sheet R DS312 April 18, 2008 Product Specification Module 1: Introduction and Ordering Information Module 3: DC and Switching Characteristics DS312-1 v3.7 April 18, 2008 DS312-3 (v3.7) April 18, 2008 • • • •

Contextual Info: DEMO KIT AVAILABLE DS31256 256-Channel, High-Throughput HDLC Controller www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS31256 Envoy is a 256-channel HDLC controller that can handle up to 60 T1 or 64 E1 data streams or two T3 data streams. Each of the 16 physical ports can handle one, two, or four

xc3s500e vq100

Contextual Info: 1 Spartan-3E FPGA Family Data Sheet DS312 July 19, 2013 Product Specification Module 1: Introduction and Ordering Information Module 3: DC and Switching Characteristics DS312 v4.1 July 19, 2013 DS312 (v4.1) July 19, 2013 • Introduction • • Features

AN399

Abstract: APP399 DS31256
Contextual Info: Maxim > App Notes > TELECOM Keywords: loopback modes, HDLC controller Mar 03, 2003 APPLICATION NOTE 399 DS31256 Loopback Modes Abstract: This application note shows how to configure various loopback modes of the DS31256 HDLC controller, and how to verify and troubleshoot as necessary.

gapped

Abstract: AN392 APP392 DS31256 TS24 E1 frame
Contextual Info: Maxim > App Notes > TELECOM Keywords: gapped clock, hdlc controller, HDLC Nov 21, 2002 APPLICATION NOTE 392 DS31256 Gapped Clock Applications Abstract: This application note discusses how to realize gapped clock applications with the DS31256 HDLC Controller.

DS9123O

Abstract: BD8 diode BCD8 c6sw MAX6954 BAV70 BAW56 MAX6955 diode matrix for LED display AB2 sot23
Contextual Info: Maxim > App Notes > DISPLAY DRIVERS Keywords: MAX6954, MAX6955, LED driver, display driver, I2C, I²C, keys, switches, keyscan, keyswitch, debounce, DS3123, DS31230, DS9123O Mar 25, 2005 APPLICATION NOTE 3462 Extending MAX6954 and MAX6955 Keyscan Beyond 32 Keys

concrete test

Abstract: H 498
Contextual Info: Flexibility & Innovation …. DS312_01 07.12.01 DATA SHEET Part Number SAW Filter 458 MHz For Pager TSF0458-L1 SPECIFICATION PRODUCT FEATURES : HIGH STABILITY LOW LOSS SMALL SIZE TEMEX S.A.W. CONTACT : PUITS-GODET 8, 2000 NEUCHÂTEL SWITZERLAND TEL. : +41 32 722 18 20

RNRZ15

Abstract: DS21352 DS2141A DS2151 DS2152 DS21552 DS21Q352 DS21Q552 DS3120 DS3120N
Contextual Info: PREMILINARY – 2/16/00 Version 3 DS3120 28 Channel T1 Framer www.dalsemi.com FEATURES • • • • • • • • • • • • • • • • • 28 T1 DS1/ISDN–PRI/J1 framing transceivers All 28 framers are fully independent Directly supports loop timing & external

MK5087

Abstract: mk5087 generator MV5087 3.58MHZ crystal oscillator
Contextual Info: GEC P L E S S E Y | s e m i c o n d u c t o r s ] DS3125-1.0 MV5087 DTMF GENERATOR The MV5087 is fabricated using ISO-CMOS high density technology and offers low power and wide voltage operation. An inexpensive 3.58MHz TV crystal completes the reference oscillator. From this frequency are derived 8 different

AN3818

Abstract: DS31256 APP3818
Contextual Info: Maxim > App Notes > T/E Carrier and Packetized Keywords: V.54 detection, Tractional-T1 Jun 20, 2006 APPLICATION NOTE 3818 Enabling Fractional-T1 FT1 Loopback Detection on the DS31256 Abstract: This application note provides the operational algorithm and coding examples to use the receive

xc3s1200e fg320

Abstract: XC3S250E vqg100 SST25LFxxxA xc3s100 LVCMOS12 XC3S500E-FT256 Macronix Lot Identifier XC3S1200E-FG320 IPL34 MX25Lxxxx
Contextual Info: Spartan-3E FPGA Family: Complete Data Sheet R DS312 November 23, 2005 Advance Product Specification Module 1: Introduction and Ordering Information Module 3: DC and Switching Characteristics DS312-1 v2.0 November 23, 2005 8 pages DS312-3 (v2.0) November 23, 2005

XC3S100E TQG144

Abstract: XC3S500E FGG320 FR 309 diode
Contextual Info: Spartan-3E FPGA Family: Complete Data Sheet R DS312 May 19, 2006 Preliminary Product Specification Module 1: Introduction and Ordering Information Module 3: DC and Switching Characteristics DS312-1 v3.0 March 22, 2006 DS312-3 (v3.2) May 19, 2006 • •

xc3s500e fg320

Abstract: xc3s500e VQG100 XC3S500E FGG320 NUMONYX xilinx bpi intel j3d XC3S250E M25PXX xc3s1600e fg320 XC3S500E DS312-3
Contextual Info: Spartan-3E FPGA Family: Data Sheet R DS312 v3.8 August 26, 2009 Product Specification Module 1: Spartan-3E FPGA Family: Introduction and Ordering Information Module 3: DC and Switching Characteristics DS312-1 (v3.8) August 26, 2009 • • • • • •

hdlc

Abstract: 08FF DS31256 AN307
Contextual Info: Maxim > App Notes > TELECOM Feb 26, 2004 Keywords: hdlc controller, test registers, HDLC, controllers APPLICATION NOTE 3071 Internal Test Registers for the DS31256 Abstract: This application note lists the internal test registers in DS31256 HDLC Controller, and explains why

DS21352

Abstract: DS2141A DS2151 DS2152 DS21552 DS21Q352 DS21Q552 DS3120 DS3120N 3of121
Contextual Info: PREMILINARY DS3120 28 Channel T1 Framer www.maxim-ic.com FEATURES § § § § § § § § § § § § § § § § § 28 T1 DS1/ISDN–PRI/J1 framing transceivers All 28 framers are fully independent Directly supports loop timing and external timing Supports H.100 / MVIP 8MHz backplanes

RNRZ15

Abstract: RNRZ11 RNRZ13 RSER20 TNRZ12
Contextual Info: PREMILINARY DS3120 28 Channel T1 Framer www.dalsemi.com FEATURES • • • • • • • • • • • • • • • • • 28 T1 DS1/ISDN–PRI/J1 framing transceivers All 28 framers are fully independent Directly supports loop timing and external

AN3345

Abstract: APP3345 hdlc DS21FF42 DS21FT42 DS21Q55 DS26528 DS3112 DS31256 DS3150
Contextual Info: Maxim/Dallas > App Notes > TELECOM Keywords: HDLC controller, framer, transceiver, T1/E1, T3/E3, hdlc, controller, t1, e1, t3, e3 Sep 09, 2004 APPLICATION NOTE 3345 Examples of DS31256 Applications App Note 3345 provides application examples for the DS31256 HDLC Controller.

0x00000146

Abstract: 070C 071C APP3347 DS31256
Contextual Info: Maxim/Dallas > App Notes > TELECOM Keywords: HDLC Controller, T3, E3, HSSI, VDSL, Unchannelized Port Sep 09, 2004 APPLICATION NOTE 3347 DS31256 Unchannelized T3/E3/HSSI/VDSL Port Configuration for Bridge Mode Applications This application note provides an example of how to configure a single T3/E3/HSSI/VDSL port for unchannelized operation on the DS31256

DS31256

Abstract: DS31256DK DS3134 LT1086 RS10
Contextual Info: DS31256DK Envoy 256-Channel, High-Throughput HDLC Controller Demo Kit www.maxim-ic.com GENERAL DESCRIPTION FEATURES § The DS31256 Envoy is a 256-channel HDLC controller capable of handling up to 64 T1 or E1 data streams or two T3 data streams. Each of the

xc3s500e fg320

Abstract: XC3S500E FGG320 XC3S250E TQG144 AT45DBX M25PXX XCF32P FOOT PRINT DS3121 AT45DBXX X2Y3 spi flash m25pxx
Contextual Info: Spartan-3E FPGA Family: Complete Data Sheet R DS312 March 21, 2005 Module 1: Introduction and Ordering Information Module 3: DC and Switching Characteristics DS312-1 v1.1 March 21, 2005 6 pages DS312-3 (v1.0) March 1, 2005 18 pages • • • • • •

Contextual Info: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS MV5089 DS3126-2.0 June 1993 MV5089 DTMF GENERATOR The MV5089 is fabricated using ISO-CMOS high density technology and offers low power and wide voltage operation. An inexpensive 3.58MHz TV crystal completes the reference

ROUND ROBIN ARBITRATION AND FIXED PRIORITY SCHEME

Abstract: Channels64 ROUND ROBIN ARBITRATION AND FIXED PRIORITY hdlc DS31256 DS3131 DS3134
Contextual Info: Application Note 2351 DS31256 and DS3134 HDLC Controller Comparisons www.maxim-ic.com INTRODUCTION This application note compares the differences between the DS3134 CHATEAU and the DS31256 Envoy HDLC controllers. The most important difference is that all known DS3134 errata have been fixed in DS31256, and the

hdlc

Abstract: DS31256
Contextual Info: Application Note 2867 Initialization Steps for the DS31256 www.maxim-ic.com INTRODUCTION By design, upon power-up the DS31256 will not take control of the PCI bus. All the physical ports ports 0 to 15 send all ones (not HDLC idle code), therefore placing the DS31256 in an idle upon power-up. On the other hand,