EP610 Search Results

EP610-30

Abstract: EP610-35 EP610-25 EP610 EP610-15 EP610-20 EP6101-10 EP610I
Contextual Info: EP610 EPLD Features * • ■ ■ ■ ■ High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tP D as fast as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs

ep610

Abstract: EP610-30 EP610-35 EP610-25 EP610-15 EP610-20 EP610I P6101
Contextual Info: EP610EPLD Features H igh -perform an ce, 16-m acrocell Classic EPLD C om binatorial speeds w ith as low as 10 ns C oun ter frequencies of up to 100 M H z Pipelined d ata rates of up to 125 M H z Program m able I / O arch itectu re w ith up to 20 inputs o r 16 ou tp uts

Contextual Info: Ml intpl 6 1992 ÌPLD610 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDs • tpo 10 ns, 100 MHz Counter Frequency w/lnternal Feedback ■ Extensive Software and Programming Support via Intel and Third Party Tools

EP610 "pin compatible"

Abstract: altera ep610
Contextual Info: bflE D ALTERA CORP • GS^S37B G0033S4 b7fl » A L T EP610A E P LD □ Features □ □ □ Preliminary Information □ □ □ Highest-performance, 16-macrocell Classic EPLD Combinatorial speeds with t PD = 7.5 ns Counter frequencies up to 125 MHz Pipelined data rates up to 142.9 MHz

altera ep610

Contextual Info: □ Features _l □ □ Advance Information J □ □ tPD Altera's EP610A Erasable Programm able Logic Device E P L D is a high­ speed version of the EP610 E P L D . It offers enhanced performance and is available in reprogrammable plastic 24-pin, 300-mil D IP ; 24-pin SO IC ; and

EP610PC-25

Abstract: EP610PC-30 16-MACROCELL EP610DC-25 EP610LI EP610PC-35 Erasable Programmable Logic Device EP610LC-30 EP610 EP610PC
Contextual Info: EP610 HIGH-PERFORMANCE 16-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3177, OCTOBER 1988-AUGUST 1989 • High-Density (Over 600 Gates) Replacement for TTL and 74HC DUAL-IN-LINE PACKAGE (TOP VIEW) • Virtually Zero Standby P ow er. . . Typ 20 pA C 1 ^ 2 4 3 vcc

Contextual Info: EP610A EPLD AN b r ^ n ^ \ High-Performance 16-Macrocell Device March 1993, ver. 2 Data Sheet Supplement □ Features □ □ □ P re lim in a ry Inform ation □ □ □ □ □ □ Highest-performance 16-macrocell Classic EPLD Combinatorial speeds with tPD = 10 ns

PLD610-10

Abstract: 85C060 D610 p EP610 "pin compatible" PLD610
Contextual Info: PLD610 PRELIMINARY CYPRESS SEMICONDUCTOR Multipurpose BiCMOS PLD Function, pin, and JEDEC compatible with EP600, EP610, EP630,85C060, and PALCE610 PLDs Very high performance — tpo = 10 ns 16 I/O macrocells, each having: — Choice of combinatorial or regis­

D85C060-25

Abstract: PLD610 85C060 P85C060-25 PLD610-25 P85C060-15 D85C060-10 intel 85C060 n85c060 pld610-15
Contextual Info: intel ¡PLD610/85C060 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610, 85C060 and 5C060 PLDs • tpD 10 ns, 100 M H z C o u n te r F req u en cy w /ln te rn a l F e e d b a c k ■ E xte n s ive S o ftw a re an d P ro g ram m in g

EP600 programming

Abstract: ple3-12a Altera EP1800 EPS448 PLE3-12 EP610 ORDERING ep1800 EP600 altera ep900 PLED448
Contextual Info: PLED/J/G P L 1 D /J/G PROGRAMMING ADAPTORS PLED/J/G FEATURES GENERAL DESCRIPTION • Programming adaptors for Altera EPS448, EP600/ EP610, EP900/EP910, EP1210, EPB1400 and EP1800/ EP1810 EPLDs. The Altera PLED/J/G 448, 600, 900, 1210, 1400 and 1800 are enhancement products allowing device pro­

ALTERA EP610

Abstract: MIL-STD-883-compliant
Contextual Info: EP610 MIL-STD-883-Compliant EPLD Features □ □ □ □ □ □ High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD = 35 ns Counter frequencies up to 28.5 MHz Pipelined data rates up to 37 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs

npld610

Abstract: NPLD610-10 PALCE610 EP610 ORDERING PLD610 DPLD610-25 intel 85C060 85C060 TNPLD610 intel PLD
Contextual Info: in tj ¡PLD610 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDa • * m - m r ' "< ^ . *. » • tpQ 10 ns, 100 MHz Counter Frequency w/lnternal Feedback ■ Ice = 105 m A max-@ 1 MHz

Contextual Info: EP610 EPLD Features High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD as low as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins

DPLD610-15

Abstract: npld610 iPLD610 PPLD610-25 PPLD610 TNPLD610 DPLD610-10 intel 85C060 NPLD610-10 PLD610
Contextual Info: in t e i ÌPLD610 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Com patible wKh EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDa • tpQ 10 ns, 100 MHz Counter Frequency w/lnternal Feedback ■ Ice = 105 mA max- @ 1 MHz ■ Programmable Low-Power Option for

EP610

Abstract: EP610-30 altera ep610 EP610-Z5 FLIPFLOP SCHEMATIC 74HC EP610-25 EP610-35 MOPE EP610-40
Contextual Info: HIGH PERFORMANCE 16 MACROCELL EPLD FEATURES CONNECTION DIAGRAM CLKl 3 n I/O Q 10[3 3 i/O □ i/o QT 3 3 3 3 3 3 3 i/o^ I/O J j j I/O Q I/O £9 1/0 0 i/o [ 0 INPUT ^ GNO ^ O EP610 The Altera EP610 Programmable Logic Device is capable of implementing over 600 equivalent gates of

Contextual Info: intel MILITARY ¡PLD610 16-MACROCELL CHMOS juPLD Function, Pin, and JEDEC Compatible with 5C060, EP600, EP610, EP630 and CE630 PLDs Programmable Clock System with 2 Synchronous Clocks and Asynchro­ nous Clocking Option on all Registers tpD 15 ns, 66 MHz Counter Frequency

EP610

Abstract: ep600i EP610-30 EP610-35 EP610-25 EP610-15 EP610-20 EP610I
Contextual Info: EP610 EPLD H igh-perform ance, 16-macrocell Classic EPLD Com binatorial speeds with t PD as low as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 100 MHz Program mable I /O architecture with up to 20 inputs or 16 outputs and 2 Clock pins

fp6102

Abstract: FP6101 EP610-30 equivalent EP610-30 FP610 EP610 TI EP610 SSI IC adder L-72 EP610-35
Contextual Info: EP610 EPLD J Features J J J J J General Description Programm able clock option for independent clocking of all registers Macrocells in d ivid u ally programmable as D, T, JK , or SR flip-flops, or for combinatorial operation Extensive third-party software and programm ing support

FC SUFFIX altera

Contextual Info: Classic EPLD Family Data Sheet M arch 1995, ver. 2 Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ Table 1. Classic Device Features Feature EP22V10 EP22V10E EPB10 EP610T EP610I EP910 EP910T EP910I EP1810 EP1810T Available gates 400 600 600 900 900 1,800 Usable gates

P85C060-25

Abstract: D85C060 PLD610-25 D85C060-25 intel 85C060 D85C060-15 IPLD610-15 EP610 ORDERING p85c060 N85C060-12
Contextual Info: INTEL CORP tIEMORY/PLD/ in t e l SbE D • HfiSblTb D077infl fl3£ ^p ÌPLD610/85C060 FAST 16-MACROCELL CMOS PLD h ITL2 ^ '^ - o 0 Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDs ■ tpo 10 ns, 100 MHz Counter Frequency

Contextual Info: EP610 EPLD □ Features □ □ □ □ □ General Description Altera's EP610 Erasable Programmable Logic Device EPLD can implement up to 600 equivalent gates of SSI and MSI logic functions. It is available in space-saving w indowed ceramic or OTP plastic 24-pin, 300-mil DIP and

Contextual Info: EP610 EPLDs High-Performance 16-Macrocell Devices Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ □ □ □ □ General Description A ltera's EP610 Erasable Programmable Logic Devices EPLDs can implement up to 600 equivalent gates of SSI and MSI logic functions in

EP630

Abstract: EP630-15 EP630-20 altera ep610 EP610A
Contextual Info: EP630 EPLD □ Features □ □ □ Altera's EP630 Erasable Programmable Logic Device EPLD is a fast, lowpow er version of the EP610 device. The EP630 EPLD can implement a 16-bit counter at up to 83 MHz and typically consumes 5 m A when operating at 1 MHz. The EP630 EPLD is available in OTP plastic 24-pin,

EP610

Abstract: MIL-STD-883-compliant TI EP610 EP610-15 PALCE610 altera ep610 ALTERA MAX 5000 programming EP610-20 EP610I
Contextual Info: EP610 EPLD Features High-performance, 16-macrocell Classic EPLD Combinatorial speeds with t PD as low as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 100 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 Clock pins