ERA60100 Search Results

Contextual Info: Ä> SPLESSE Y e m ic o n d u c to rs , NOVEMBER 1989 ADVANCE INFORMATION ERA60100 ELECTRICALLY RECONFIGURABLE ARRAY - ERA Supersedes April 1989 edition The ERA60100 isthefirst in a new family of Field Program­ mable Gate ArraysfromPlessey Semiconductors. Engineers

ERA60100/BH/HC84

Contextual Info: p PL1ESSEY APR,L199° SEM IC O N D U C TO R S = ERA60100 ELECTRICALLY RECONFIGURABLE ARRAY - ERA Supersedes November 1989 edition The ERA60100 isthe first in a newfamily of Field Program­ mable Gate Arrays from Piessey Semiconductors. Engineers can capture and simulate their logic and route their design to

Contextual Info: ERA60100 Fig.3 depicts two core cells with their available interconnect resources shown connected to dual 4 to 1 line data selectors. The selectors are controlled by the RAM to route the two selected input lines through to the logic. The ‘inverter’ control connects the two gate inputs together

Contextual Info: PDSP16350 SK3NAL DESCRIPTION DIN33:0 Data bus forthe input register. This input register provides a 34 bit, incremental or absolute, phase value, if the mode pin is low. Alternatively if the mode pin is high, it provides an 18 bit phase increment value, via D17:0, and a 16 bit scale value via D33:18.