JANUARY1995 Search Results

V68MLA1206T23

Abstract: V14MLA0805 V14MLA0805L V14MLA1206 V18MLA0805 V18MLA0805L .MODEL BD231
Contextual Info: S ML Series HARRIS S E M I C O N D U C T O R Multilayer Surface Mount Transient Surge Suppressors January1995 Features • Leadless Chip Form - “Zero” Lead Inductance • Multilayer Construction Technology • -55°C to +125°C Operating Temperature Range

Contextual Info: HA5023/883 S Dual 125MHz Video Current Feedback Amplifier January1995 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • Wide Unity Gain B andw idth. 125MHz

80c196nu

Abstract: p6506
Contextual Info: in te i M W Ä ß C ii D iF !ì» T M 80C196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER 50 MHz Operation* 1 Mbyte of Linear Address Space 1000 Bytes of Register RAM Register-register Architecture Footprint and Functionally Compatible with the 80C196NP 2x the Performance of the 80C196NP

45l50

Abstract: V53C104H
Contextual Info: M O S E L V I T E L IC V53C104H U LTR A -H IG H PERFO RM ANCE, L O W P O W ER 2 5 6 K X 4 B IT F A S T P A G E M O D E CM O S D YN A M IC R A M HIGH PERFORMANCE 45/45L 50/50L 55/55L 60/60L Max. RAS Access Time, 1RAC 45 ns 50 ns 55 ns 60 ns Max. Column Address Access Time, (tCAA)

Contextual Info: M O S E L V IT E L IC V100J9 and V100J8 1M X 9, 1M X 8 BIT FAST PAGE MODE CMOS DYNAMIC RAM MEMORY MODULE 60/60L 70/70L 80/80L Max. RAS Access Time, tRAf0 HIGH PERFORMANCE V100J8/9 60 ns 70 ns 80 ns Max. Column Address Access Time, (trA A 30 ns 35 ns 40 ns

Contextual Info: M O SEL VTTEUC PRELIMINARY V104J232 512K x 32 SIMM Features Description 524,288 x 32 bit organizations Utilizes 256K x 4 CMOS DRAMs Fast access times 70 ns, 80 ns, 100 ns Fast Page mode operation Low power dissipation _ CAS before RAS refresh, RAS only refresh, and

Contextual Info: M O SEL V tTE LiC V53C8512N 3.3 VOLT, LO W POWER 512K x 8 AN D 5 1 2 K x 9 B IT FA S T PAGE MODE CMOS DYNAMIC RAM PRELIM INARY HIGH PERFORMANCE V53C8512N 60/60L 70/70L M ax. R A S A cce ss T im e, Orac 6 0 ns 70 ns M ax. C o lum n A d dre ss A cce ss T im e , tCAA)

Contextual Info: M O S EL V IT E L IC V53C 16258H 2 5 6 K X 16 P A G E M O D E C M O S D Y N A M IC R A M W ITH E X T E N D E D D A TA O U T P U T HIGH PERFORMANCE P R E LIM IN A R Y 45 50 55 60 Max. RAS Access Time, tRAc 45 ns 50 ns 55 ns 60 ns Max. Column Address Access Time, (tCAA)

Contextual Info: M O S E L V TTE U C PRELIMINARY V104J32 256K x 32 SIMM Features Description • ■ ■ ■ ■ ■ The V 104J32 Mem ory Module is organized as 262,144 x 32 bits in a 72-lead single-in-line module. The 256K x 32 memory module uses 8 Mosel-Viteiic 256K x 4 DRAMs. The x32 modules are ideal for use

V53C1625BH

Contextual Info: M O SEL V IT E U C V53C16258H 256K X 16 PAG E MODE CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT HIGH PERFORMANCE PRELIMINARY 45 50 55 60 Max. RAS Access Time, tRAC 45 ns 50 ns 55 ns 60 ns Max. Column Address Access Time, Ocaa) 22 ns 25 ns 28 ns 30 ns Min. Extended Data Out Page Mode Cycle Time, (tPC)

Contextual Info: M O S E L V 1T E U C V53C104F HIGH PERFORMANCE, LOW POWER 256K X 4 BIT FAST PAGE MODE CMOS DYNAMIC RAM HIGH PERFORMANCE V53C104F Max. RAS Access Tim e, tRAC 60/60L 70/70L 80/80L 60 ns 70 ns 8 0 ns Max. Column Address Access Tim e, (tCAA) 3 0 ns 35 ns 4 0 ns

H7555

Abstract: HEF4516
Contextual Info: HEF4516B J I BINARY UP/DOWN COUNTER T h e H E F 4 5 1 6 B is an edge-triggered synchronous u p /d o w n 4 -b it b inary co u n ter w ith a clo ck in p u t C P , an u p /d o w n c o u n t co ntrol in p u t (U P /D N ), an active LO W c o u n t enable n p u t (C E ), an

V53C1OON

Contextual Info: M O S E L V IT E L IC V53C100N HIGH PERFORMANCE, 3.3 VOLT 1M X 1 BIT FAST PAGE MODE CMOS DYNAMIC RAM 60/60L 70/70L 80/80L 60 ns 70 ns 80 ns Max. Column Address Access Time, tCAA 35 ns 40 ns 45 ns Max. CAS Access Time, (tCAC) 20 ns 25 ns 25 ns Min. Fast Page Mode Cycle Time, (1p c )

V53C85

Contextual Info: M O SEL V iT E U C V53C8512 HIGH PERFORMANCE, LOW POWER 512K x 8 FAST PAGE MODE CMOS DYNAMIC RAM HIGH PERFORMANCE V53C8512 PRELIMINARY 50/S0L 60/60L 70/70L Max. RAS Access Time, tRAc 50 ns 60 ns 70 ns Max. Column Address Access Time, (1CAA) 25 ns 30 ns 35 ns

52C8128

Abstract: V52C8128
Contextual Info: M O SEL V tT E U C V52C8128 MULTIPORT VIDEO RAM WITH 128K X 8 DRAM AND 256 X 8 SAM 70 80 10 Max. RAS Access Time, tRAC 70 ns 80 ns 100 ns Max. CAS Access Time, (tCAC) 20 ns 25 ns 25 ns Max. Column Address Access Time, ( t ^ ) 35 ns 40 ns 50 ns Min. Fast Page Mode Cycle Time, (tPC)

Contextual Info: M O S E L V IT E L IC V53C8512 HIGH PERFORMANCE, LOW POWER 512K x 8 FAST PAGE MODE CMOS DYNAMIC RAM PRELIMINARY 50/50L 60/60L 70/70L Max. RAS Access Time, Ìrac 50 ns 60 ns 70 ns Max. Column Address Access Time, <tCAA) 25 ns 30 ns 35 ns Min. Fast Page Mode Cycle Time, (tpc)

Contextual Info: M O S E L V IT E L IC V53C664A 64K x 16 B IT FA ST PAGE MODE BYTE WRITE CMOS DYNAMIC RAM 60/60L 70/70L 80/80L Max. RAS Access Time, tR A r 60 ns 70 ns 80 ns Max. Column Address Access Time, (tr l 4 ) 35 ns 40 ns 45 ns Min. Fast Page Mode Cycle Time, (tp r )