MU9C1640 Search Results

Contextual Info: MU9C1640 CacheCAM S E M I C O N D U C T O R S 'OR DISTINCTIVE CHARACTERISTICS Vertical cascading and system flag generation require no external logic 1 K X 64-bit C M O S C ontent-add ressable M em o ry C AM M em ory A rray w idth can be configured as a m ixture of CAM

Contextual Info: MU9C1640 CacheCAM The Status Register Bit Assignments as shown in Table 6 on page 9 of the MU9C1640 Data Sheet Rev. 1, dated October 21, 1994, and in Table 6 on page E-9 of the CAMLAB Development Reference Manual Rev. 0, dated January 1995, are incorrect. The corrected Table 6 is shown below:

JL - 012C

Contextual Info: DISTINCTIVE CHARACTERISTICS 1024 X 64-bit Content-addressable Memory CAM Architecture similar to the industry standard MU9C1480 LANCAM for ease of use Patented Associated Data feature allows storage of related data with each CAM entry that is immediately

Contextual Info: DISTINCTIVE CHARACTERISTICS 1024 X 64-bit Content-addressable Memory CAM Architecture similar to the industry standard MU9C1480 LANCAM for ease of use Patented Associated Data feature allows storage of related data with each CAM entry that is immediately

0309H

Contextual Info: *4 Î99S DISTINCTIVE CHARACTERISTICS 1K X 64-bit CMOS Content-addressable Memory CAM Vertical cascading and system flag generation require no external logic Memory Array width can be configured as a mixture of CAM and RAM on 16-bit boundaries to provide a flexible