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pd0008

Abstract: tray 8 x 8 TSOP TRAY 40 PIN TSOP package tray N1N213 Package and Packing Information ST
Contextual Info: PD0008 Packing information Tray for TSOP packages type 1 Introduction TSOP type-1 packages can be supplied in tray packing. Refer to Table 1 for the list of TSOP type-1 packages supplied in trays. The objective of this document is provide a detailed description of the tray. It applies to all

Contextual Info: * 16-INPUT MULTIPLEXER SYNERGY SY100S364 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 1300ps The SY100S364 is a 16-input m ultiplexer designed for use in high-perform ance ECL system s. The four Data Select inputs So, S i , S 2 , S 3 determ ine the bit from the 16

Contextual Info: TRIPLE 4-INPUT MULTIPLEXER WITH ENABLE SYNERG Y SY100S371 SEMICONDUCTOR DESCRIPTION FEATURES Max. propagation delay of 1000ps I e e min. of-68m A The SY100S371 is an ultra-fast triple 4-input multiplexer with true and complementary outputs designed for use in

Contextual Info: >0 » 9-BIT ECL-TO-TTL WITH 3-STATE ENABLE SYNERG Y SY10H601 SY100H601 SEMICONDUCTOR DESCRIPTION FEATURES 9-bit ideal for byte-parity applications 3-state TTL outputs Flow-through configuration Extra TTL and ECL power/ground pins to minimize switching noise

Contextual Info: * SYNERGY REGISTERED HEX TTL-TO-PECL SY10H606 SY100H606 SEMICONDUCTOR DESCRIPTION FEATURES • Differential 50fì ECL outputs ■ Choice between differential PECL or TTL clock input ■ Single +5V power supply ■ V bb output for single-ended use ■ Multiple power and ground pins to minimize noise

Contextual Info: * SY10E142 SY100E142 9-BIT SHIFT REGISTER SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION 700MHz min. shift frequency Extended 100E V ee range of -4.2V to -5.5V 9 bits wide for byte-parity applications Asynchronous Master Reset Dual clocks Fully compatible with industry standard 10KH,

Contextual Info: * SYNERGY LOW-POWER HEX TTL-TO-PECL TRANSLATOR SY100S391 SEMICONDUCTOR DESCRIPTION FEATURES Operates from a single +5V supply Differential PECL outputs Companion chip to SY100S390 PECL-to-TTL translator Function and pinout compatible with National and Signetics F100K

Contextual Info: * 3-BIT SCANNABLE REGISTERED BUS e V A IC D ^ U S w N C n G w SEMICONDUCTOR SY10E337 SY100E337 T R A N Q P F IV F R n A N o U tlv tn FEATURES DESCRIPTION 1500ps max. clock to bus data transmit 1000ps max. clock to Q (data receive) Extended 100E V ee range of -4.2V to -5.5V

Contextual Info: V SYNERGY 5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER w/o ENABLE SEMICONDUCTOR FEATURES • 3.3V and 5V power supply options ■ 200ps part-to-part skew ■ 50ps output-to-output skew ■ Differential design ■ V bb output ■ Voltage and temperature compensated outputs

Contextual Info: * QUINT DIFFERENTIAL LINE RECEIVER SYNERGY SY10E116 SY100E116 SEMICONDUCTOR DESCRIPTION FEATURES 450ps max. Propagation Delay Extended 100E V e e range of -4.2V to -5.5V V bb output for single-ended reception Fully compatible with industry standard 10KH, 100K I/O levels

B420

Abstract: AOB420 D2PAK to-263 omega AOB420L
Contextual Info: Rev 2: Oct 2004 AOB420, AOB420L Green Product N-Channel Enhancement Mode Field Effect Transistor General Description Features The AOB420 uses advanced trench technology to provide excellent RDS(ON), low gate chargeand low gate resistance. This device is ideally suited for use

Contextual Info: * SYNERGY SEMICONDUCTOR 1:9 DIFFERENTIAL CLOCK DRIVER WITH ENABLE FEATURES • Low skew ■ Extended 100E V ee range of -4.2V to -5.5V ■ Guaranteed skew limits ■ Differential design ■ V bb output ■ Enable input ■ Fully compatible with industry standard 10KH, 100K

Contextual Info: * SYNERGY SEMICONDUCTOR 125 MHz WRITE PROGRAMMABLE TIMING EDGE VERNIER FEATURES SY605 DESCRIPTION True 125MHz retrigger rate Synergy's SY605 is an ECL-compatible tinning vernier delay generator whose time delay is programmed via an 8bit code which is loaded via an independent "WRITE" input.

Contextual Info: * SYNERGY 9-BIT MAGNITUDE COMPARATOR SY10E166 SY100E166 SEMICONDUCTOR FEATURES DESCRIPTION 1100ps max. Propagation Delay A = B Extended 100E V ee range of -4.2V to -5.5V Fully compatible with industry standard 10KH, 100K ECL levels The SY10/100E166 are 9-bit magnitude comparators

Contextual Info: * SYNERG Y SY10E155 SY100E155 6-BIT2:1 MUX-LATCH SEMICONDUCTOR FEATURES 750ps max. LEN to output Extended 100E V ee range of -4.2V to -5.5V 700ps max. D to output Single-ended outputs Asynchronous Master Reset Dual latch-enables Fully compatible with industry standard 10KH,

Contextual Info: * SY10E157 SY100E157 QUAD 2:1 MULTIPLEXER SYNERGY SEMICONDUCTOR FEATURES • ■ Individual select controls DESCRIPTION The SY10/100E157 contain four 2:1 m ultiplexers with differential outputs. The output data are controlled by the individual Select SEL inputs. The individual select

Contextual Info: * SYNERGY 12-BIT PARITY GENERATOR/CHECKER SY10E160 SY100E160 SEMICONDUCTOR DESCRIPTION FEATURES Provides odd-HIGH parity of 12 inputs Extended 100E Vee range of -4.2V to -5.5V Output register with Shift/Hold capability 900ps max. D to QId output Enable control

Contextual Info: * SYNERGY SEMICONDUCTOR QUAD 4-INPUT OR/NOR GATE FEATURES • 500ps max. propagation delay ■ Extended 100E V ee range of -4.2V to -5.5V ■ True and complementary outputs SY10E101 SY100E101 DESCRIPTION The SY10/100E101 are quad 4-input OR/NOR gates designed for use in new, high-performance ECL systems.

Contextual Info: * SY10E150 SY100E150 6-BIT D LATCH SYNERGY SEMICONDUCTOR FEATURES • ■ 700ps max. propagation delay DESCRIPTION The SY10/100E150 are 6-bit D latches with differential outputs designed for use in new, high- perform ance ECL system s. W hen both Latch Enables L E N i, LEN 2 are at a

Contextual Info: * _ 8-INPUT PECL DIFFERENTIAL MUX WITH TTL SELECTS SYNERGY SY100S863 SEMICONDUCTOR DESCRIPTION FEATURES • Low skew ■ Differential PECL inputs ■ Differential cut-off PECL outputs capable of driving 25fì load for driving data bus ■ Tri-state TTL output

Contextual Info: « SYNERGY HEX D-LATCH SY100S350 SEMICONDUCTOR FEATURES • Max. transparent propagation delay of 900ps ■ Min. Master Reset and Enable pulse widths of 100ps ■ Ie e min. of -98m A ■ Industry standard 100K ECL levels ■ Extended supply voltage option:

Contextual Info: « SY100S331 TRIPLE D FLIP-FLOP SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION Max. toggle frequency of 800MHz The SY100S331 offers three D-type, edge-triggered m aster/slave flip-flops with true and com plem ent outputs, designed for use in high-perform ance ECL system s. Each

Contextual Info: * SYNERGY 9-BIT LATCH WITH PARITY SY10E175 SY100E175 SEMICONDUCTOR FEATURES • 9-bit latch ■ Extended 100E V ee range of - 4 .2 V to - 5 .5 V ■ Parity detection/generation ■ 800ps max. D to Output ■ Reset ■ Internal 75KH input pull-down resistors

Contextual Info: * FEATURES DESCRIPTION Max. propagation delay of 700ps Ie e SY100S322 9-BIT BUFFER SYNERGY SEMICONDUCTOR The SY100S322 is an ultra-fast buffer designed for use in high-perform ance ECL system s. The device provides nine non-inverting buffers with single-ended outputs. The