SN74AS30 Search Results

sn74as306

Contextual Info: SN74AS305 OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER D3SM, JUNE 1990 - REVISED SEPTEMBER 1990 Maximum Output Skew of 1 ns D OR N PACKAGE {TOP VIEW Maximum Pulse Skew of 1 n* 03 [ Center Pin Vcc and GND Configurations Minimize High-Speed Switching Noise U 04 [ 2

Contextual Info: SN74AS305 OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER D3596, JUNE 1990 D OR N PACKAGE CTOP VIEW Maximum Output Skew of 1 ns Maximum Pulse Skew of 1 ns Center Pin Vc c and GND Configurations Minimize High-Speed Switching Noise Package Options Include Plastic “Small

Contextual Info: SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30 8-INPUT POSITIVE-NAND GATES SDAS010B – MARCH 1984 – REVISED DECEMBER 1994 SN54ALS30A, SN54AS30 . . . J PACKAGE SN74ALS30A, SN74AS30 . . . D OR N PACKAGE TOP VIEW Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip

75285

Abstract: SN74AS303
Contextual Info: SN74AS303 OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER 03543, JULY 1990 Maximum Output Skew of 1 ns SN74AS303 . . . D t OR N PACKAGE TOP VIEW Maximum Pulse Skew of 1 ns 1 16 ] Q 2 Q 4[ 2 15 ] Q 1 Q 3[ Center-Pin V qc and GND Configurations Minimize High-Speed Switching Noise

CDC304

Abstract: SN74AS304
Contextual Info: CDC304 OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER SCAS325A – JULY 1990 – REVISED NOVEMBER 1995 D D D D D D D OR N PACKAGE TOP VIEW Replaces SN74AS304 Maximum Output Skew of 1 ns Maximum Pulse Skew of 1.5 ns TTL-Compatible Inputs and Outputs Center-Pin VCC and GND Configurations

Contextual Info: SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30 8-INPUT POSITIVE-NAND GATES SDAS010C – MARCH 1984 – REVISED NOVEMBER 2000 SN54ALS30A, SN54AS30 . . . J PACKAGE SN74ALS30A, SN74AS30 . . . D OR N PACKAGE SN74AS30 . . . DB PACKAGE TOP VIEW description These devices contain an 8-input positive-NAND

SN54ALS30A

Abstract: SN54AS30 SN74ALS30A SN74ALS30AD SN74ALS30AN SN74AS30 SN74AS30D SN74AS30DBR SN74AS30N
Contextual Info: SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30 8-INPUT POSITIVE-NAND GATES SDAS010C – MARCH 1984 – REVISED NOVEMBER 2000 SN54ALS30A, SN54AS30 . . . J PACKAGE SN74ALS30A, SN74AS30 . . . D OR N PACKAGE SN74AS30 . . . DB PACKAGE TOP VIEW description These devices contain an 8-input positive-NAND

CDC305

Abstract: SN74AS305
Contextual Info: CDC305 OCTAL DIVIDEĆBYĆ2 CIRCUIT/CLOCK DRIVER SCAS326A − JUNE 1990 − REVISED NOVEMBER 1995 D D D D D D D OR N PACKAGE TOP VIEW Replaces SN74AS305 Maximum Output Skew of 1 ns Maximum Pulse Skew of 1 ns TTL-Compatible Inputs and Outputs Center-Pin VCC and GND Configurations

Contextual Info: SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30 www.ti.com . SDAS010D – APRIL 1982 – REVISED APRIL 2009

SN74AS304

Contextual Info: SN74AS304 OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER D3555. JULY 1990 * Maximum Output Skew of 1 ns * Maximum Pulse Skew of 1 ns * Center-Pin V cc and GND Configurations Minimize High-Speed Switching Noise

SN74AS303D

Abstract: SN74AS303N SN74AS303
Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2005 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74AS303D OBSOLETE SOIC D 16 TBD Call TI Call TI SN74AS303N OBSOLETE PDIP N 16 TBD Call TI Call TI

Contextual Info: SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30 8-INPUT POSITIVE-NAND GATES SDAS010C – MARCH 1984 – REVISED NOVEMBER 2000 SN54ALS30A, SN54AS30 . . . J PACKAGE SN74ALS30A, SN74AS30 . . . D OR N PACKAGE SN74AS30 . . . DB PACKAGE TOP VIEW description These devices contain an 8-input positive-NAND

CDC305

Abstract: SN74AS305
Contextual Info: CDC305 OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995 D D D D D D D OR N PACKAGE TOP VIEW Replaces SN74AS305 Maximum Output Skew of 1 ns Maximum Pulse Skew of 1 ns TTL-Compatible Inputs and Outputs Center-Pin VCC and GND Configurations

Contextual Info: SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30 www.ti.com . SDAS010D – APRIL 1982 – REVISED APRIL 2009

CHOA

Contextual Info: SN74ALS30A, SN74AS30, SN54ALS30A, SN54AS30 8-INPUT POSITIVE-NAND GATES MARCH 1984 - REVISED MAY 1986 • • SN S4A LS30A . SN 54A S30 J PACKAG E SN 74A LS30A . S N 74 A S3 0 . . . D OR N PACKAG E Package O ptions Include Plastic "S m a ll O u tlin e" Packages, Ceram ic Chip Carriers,

SN74AS303

Contextual Info: CDC303 OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER SCAS323 - JULY 1990 - REVISED MARCH 1994 D OR N PACKAGE TOP VIEW Replaces SN74AS303 Maximum Output Skew Between Same Phase Outputs of 1 ns Maximum Pulse Skew of 1 ns TTL-Compatible Inputs and Outputs Center-Pin Vcc and GND Configurations

SN74AS303

Contextual Info: SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30 www.ti.com . SDAS010D – APRIL 1982 – REVISED APRIL 2009

SN74AS303

Abstract: CDC303
Contextual Info: CDC303 OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER SCAS323A – JULY 1990 – REVISED NOVEMBER 1995 D D D D D D D OR N PACKAGE TOP VIEW Replaces SN74AS303 Maximum Output Skew Between Same Phase Outputs of 1 ns Maximum Pulse Skew of 1 ns TTL-Compatible Inputs and Outputs

SN74AS303

Abstract: CDC303 CDC303D CDC303DR
Contextual Info: CDC303 OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER SCAS323A – JULY 1990 – REVISED NOVEMBER 1995 D D D D D D D OR N PACKAGE TOP VIEW Replaces SN74AS303 Maximum Output Skew Between Same Phase Outputs of 1 ns Maximum Pulse Skew of 1 ns TTL-Compatible Inputs and Outputs

Contextual Info: SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30 8-INPUT POSITIVE-NAND GATES SDAS010C – MARCH 1984 – REVISED NOVEMBER 2000 SN54ALS30A, SN54AS30 . . . J PACKAGE SN74ALS30A, SN74AS30 . . . D OR N PACKAGE SN74AS30 . . . DB PACKAGE TOP VIEW description These devices contain an 8-input positive-NAND

SN54AS30

Contextual Info: SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30 8-INPUT POSITIVE-NAND GATES SDAS010B - MARCH 1984 - REVISED DECEMBER 1994 * Package Options Include Plastic Small-Outline D Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

Contextual Info: SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30 www.ti.com SDAS010E – APRIL 1982 – REVISED OCTOBER 2012 8-INPUT POSITIVE-NAND GATES Check for Samples: SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30 FEATURES 1 8-Input Positive-NAND Gates Available in J, DW, N, and FK Packages

SN54ALS30A

Abstract: SN54AS30 SN74ALS30A SN74ALS30AD SN74ALS30AN SN74AS30 SN74AS30D SN74AS30DBR SN74AS30N
Contextual Info: SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30 8-INPUT POSITIVE-NAND GATES SDAS010C – MARCH 1984 – REVISED NOVEMBER 2000 SN54ALS30A, SN54AS30 . . . J PACKAGE SN74ALS30A, SN74AS30 . . . D OR N PACKAGE SN74AS30 . . . DB PACKAGE TOP VIEW description These devices contain an 8-input positive-NAND

Contextual Info: SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30 www.ti.com . SDAS010D – APRIL 1982 – REVISED APRIL 2009