SN74LV164 Search Results

Contextual Info: SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403D – APRIL 1998 – REVISED JANUARY 2001 D D D D SN54LV164A . . . J OR W PACKAGE SN74LV164A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)

A115-A

Abstract: C101 SN54LV164A SN74LV164A
Contextual Info: SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403D – APRIL 1998 – REVISED JANUARY 2001 D D D D SN54LV164A . . . J OR W PACKAGE SN74LV164A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)

LV164A

Abstract: A115-A C101 SN54LV164A SN74LV164A
Contextual Info: SN54LV164A, SN74LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403G − APRIL 1998 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF

Contextual Info: SN54LV164A, SN74LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE

Contextual Info: SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE CLR CLK

Contextual Info: SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE CLR CLK

A115-A

Abstract: C101 SN54LV164A SN74LV164A
Contextual Info: SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403E – APRIL 1998 – REVISED JUNE 2003 1 2 14 13 3 12 4 11 5 10 6 9 7 8 VCC QH QG QF QE CLR CLK B QA QB QC QD 14 B A NC VCC QH 1 2 13 QH 3 12 QG 11 QF 4 SN54LV164A . . . FK PACKAGE TOP VIEW

Contextual Info: SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D Latch-Up Performance Exceeds 250 mA Per D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 2 13 3

A115-A

Abstract: C101 SN54LV164A SN74LV164A
Contextual Info: SN54LV164A, SN74LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE

Contextual Info: SN54LV164A, SN74LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE

SN54LV164A

Abstract: SN74LV164A A115-A C101 LV164
Contextual Info: SN54LV164A, SN74LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE

A115-A

Abstract: C101 SN54LV164A SN74LV164A LV164A
Contextual Info: SN54LV164A, SN74LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403G − APRIL 1998 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF

A115-A

Abstract: C101 SN54LV164A SN74LV164A
Contextual Info: SN54LV164A, SN74LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE

Contextual Info: SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403C – APRIL 1998 – REVISED MAY 2000 D D D D D D description The ’LV164A devices are 8-bit parallel-out serial shift registers designed for 2-V to 5.5-V VCC operation. SN54LV164A . . . J OR W PACKAGE

Contextual Info: SN54LV164A, SN74LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE

Contextual Info: SN54LV164A, SN74LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE

SN54LV164A

Abstract: SN74LV164A
Contextual Info: SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403B – APRIL 1998 – REVISED JUNE 1998 D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV164, SN74LV164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS _ SCLS191B - FEBRUARY 1993 - R EVISED APRIL 1996 • E P IC Enhanced-Performance Implanted CMOS • • • • • 2-(X SN54LV164. j or w package . .^db.orpw package

SN54LV164

Contextual Info: SN54LV164, SN74LV164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS191B – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV164A, SN74LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE

Contextual Info: SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE CLR CLK

A115-A

Abstract: C101 SN54LV164A SN74LV164A
Contextual Info: SN54LV164A, SN74LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE

Contextual Info: SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE CLR CLK

A115-A

Abstract: C101 SN54LV164A SN74LV164A
Contextual Info: SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403D – APRIL 1998 – REVISED JANUARY 2001 D D D D SN54LV164A . . . J OR W PACKAGE SN74LV164A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)