A115-A
Abstract: C101 LV165A SN54LV165A SN74LV165A SN74LV165APWRG3
Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A
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SN54LV165A,
SN74LV165A
SCLS402M
000-V
A114-A)
A115-A)
SN54LV165A
A115-A
C101
LV165A
SN54LV165A
SN74LV165A
SN74LV165APWRG3
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Untitled
Abstract: No abstract text available
Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402L − APRIL 1998 − REVISED MAY 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A
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PDF
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SN54LV165A,
SN74LV165A
SCLS402L
000-V
A114-A)
A115-A)
SN54LV165A
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lv165a
Abstract: No abstract text available
Text: SN54LV165A, SN74LV165A www.ti.com SCLS402N – APRIL 1998 – REVISED JULY 2013 PARALLEL-LOAD 8-BIT SHIFT REGISTERS Check for Samples: SN54LV165A, SN74LV165A FEATURES DESCRIPTION • • • The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation.
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SN54LV165A,
SN74LV165A
SCLS402N
LV165A
000-V
A114-A)
A115-A)
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Untitled
Abstract: No abstract text available
Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode
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SN54LV165A,
SN74LV165A
SCLS402K
000-V
A114-A)
A115-A)
SN54LV165A
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Untitled
Abstract: No abstract text available
Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A
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Original
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PDF
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SN54LV165A,
SN74LV165A
SCLS402M
000-V
A114-A)
A115-A)
SN54LV165A
|
Untitled
Abstract: No abstract text available
Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode
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PDF
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SN54LV165A,
SN74LV165A
SCLS402K
000-V
A114-A)
A115-A)
SN54LV165A
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Untitled
Abstract: No abstract text available
Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode Operation
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PDF
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SN54LV165A,
SN74LV165A
SCLS402K
000-V
A114-A)
A115-A)
SN54LV165A
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Untitled
Abstract: No abstract text available
Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A
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PDF
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SN54LV165A,
SN74LV165A
SCLS402M
000-V
A114-A)
A115-A)
SN54LV165A
|
Untitled
Abstract: No abstract text available
Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D Latch-Up Performance Exceeds 250 mA Per D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D JESD 17
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PDF
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SN54LV165A,
SN74LV165A
SCLS402M
000-V
A114-A)
A115-A)
SN54LV165A
|
Untitled
Abstract: No abstract text available
Text: SN54LV165A, SN74LV165A www.ti.com SCLS402N – APRIL 1998 – REVISED JULY 2013 PARALLEL-LOAD 8-BIT SHIFT REGISTERS Check for Samples: SN54LV165A, SN74LV165A FEATURES DESCRIPTION • • • The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation.
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SN54LV165A,
SN74LV165A
SCLS402N
000-V
A114-A)
A115-A)
LV165A
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A115-A
Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode
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Original
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PDF
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SN54LV165A,
SN74LV165A
SCLS402K
SN54LV165A
A115-A
C101
SN54LV165A
SN74LV165A
SN74LV165ARGYR
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Untitled
Abstract: No abstract text available
Text: SN54LV165A, SN74LV165A www.ti.com SCLS402N – APRIL 1998 – REVISED JULY 2013 PARALLEL-LOAD 8-BIT SHIFT REGISTERS Check for Samples: SN54LV165A, SN74LV165A FEATURES DESCRIPTION • • • The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation.
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SN54LV165A,
SN74LV165A
SCLS402N
LV165A
000-V
A114-A)
A115-A)
|
74LV165A
Abstract: No abstract text available
Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A
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Original
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PDF
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SN54LV165A,
SN74LV165A
SCLS402M
000-V
A114-A)
A115-A)
SN54LV165A
74LV165A
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Untitled
Abstract: No abstract text available
Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A
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Original
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PDF
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SN54LV165A,
SN74LV165A
SCLS402M
000-V
A114-A)
A115-A)
SN54LV165A
|
|
Untitled
Abstract: No abstract text available
Text: SN54LV165A, SN74LV165A www.ti.com SCLS402N – APRIL 1998 – REVISED JULY 2013 PARALLEL-LOAD 8-BIT SHIFT REGISTERS Check for Samples: SN54LV165A, SN74LV165A FEATURES DESCRIPTION • • • The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation.
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Original
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SN54LV165A,
SN74LV165A
SCLS402N
LV165A
000-V
A114-A)
A115-A)
|
Untitled
Abstract: No abstract text available
Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A
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Original
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PDF
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SN54LV165A,
SN74LV165A
SCLS402M
000-V
A114-A)
A115-A)
SN54LV165A
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Untitled
Abstract: No abstract text available
Text: SN54LV165A, SN74LV165A www.ti.com SCLS402N – APRIL 1998 – REVISED JULY 2013 PARALLEL-LOAD 8-BIT SHIFT REGISTERS Check for Samples: SN54LV165A, SN74LV165A FEATURES DESCRIPTION • • • The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation.
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Original
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SN54LV165A,
SN74LV165A
SCLS402N
LV165A
000-V
A114-A)
A115-A)
|
A115-A
Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode
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Original
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PDF
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SN54LV165A,
SN74LV165A
SCLS402K
SN54LV165A
A115-A
C101
SN54LV165A
SN74LV165A
SN74LV165ARGYR
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Untitled
Abstract: No abstract text available
Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A
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Original
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PDF
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SN54LV165A,
SN74LV165A
SCLS402M
000-V
A114-A)
A115-A)
SN54LV165A
|
sh dlp
Abstract: No abstract text available
Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A
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Original
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PDF
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SN54LV165A,
SN74LV165A
SCLS402M
000-V
A114-A)
A115-A)
SN54LV165A
sh dlp
|
Untitled
Abstract: No abstract text available
Text: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode
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Original
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PDF
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SN54LV165A,
SN74LV165A
SCLS402K
000-V
A114-A)
A115-A)
SN54LV165A
|
Untitled
Abstract: No abstract text available
Text: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A
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Original
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PDF
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SN54LV165A,
SN74LV165A
SCLS402M
000-V
A114-A)
A115-A)
SN54LV165A
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