SN74LVC1G00A Search Results

Contextual Info: SN74LVC1G00A SINGLE 2-INPUT POSITIVE-NAND GATE SCAS609 – JUNE 1998 D EPIC Enhanced-Performance Implanted D D D D DBV OR DCK PACKAGE (TOP VIEW CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN74LVC1G00A SINGLE 2-INPUT POSITIVE-NAND GATE SC AS609 - JU NE 1998 • EPIC Enhanced-Performance Implanted CMOS Subm icron Process • Typical V q lp (O utput Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C • Typical Vq hv DBV OR DCK PACKAGE (TOP VIEW)

Contextual Info: Contents SN74LVC1G00A Page Single 2-Input Positive-NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 LVC Single Gates SN74LVC1G02A Single 2-Input Positive-NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

Contextual Info: SN74LVC1G00A SINGLE 2-INPUT POSITIVE-NAND GATE S C A S 6 0 9 - JU NE 1998 • EPIC Enhanced-Performance Implanted • Typical Vq l p (Output Ground Bounce < 0.8 V at VCc = 3.3 V, TA = 25°C • Typical Vq h v (Output Vq h Undershoot) > 2 V at VCc = 3.3 V, TA = 25°C

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Abstract: SN74HC1G00 SCAD001D sn74154 SN74ALVC1G32 JK flip flop IC SDFD001B philips 18504 FB 3306 CMOS Data Book Texas Instruments Incorporated
Contextual Info: W O R L D L Logic Selection Guide August 1998 E A D E R I N L O G I C P R O D U C T S LOGIC OVERVIEW 1 FUNCTIONAL INDEX 2 FUNCTIONAL CROSSĆREFERENCE 3 DEVICE SELECTION GUIDE 4 3 LOGIC SELECTION GUIDE AUGUST 1998 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or