SN74S112A |
|
Texas Instruments
|
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR |
Original |
PDF
|
712.55KB |
17 |
SN74S112A |
|
Texas Instruments
|
DUAL J-K NEGATIVE EDGE TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR |
Original |
PDF
|
309.89KB |
9 |
SN74S112AD |
|
Texas Instruments
|
SN74S112 - Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70 |
Original |
PDF
|
1.34MB |
19 |
SN74S112AD |
|
Texas Instruments
|
Dual J-K Negative-Edge-Triggered Flip-Flop with Preset and Clear |
Original |
PDF
|
309.88KB |
9 |
SN74S112AD |
|
Texas Instruments
|
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70 |
Original |
PDF
|
864.89KB |
20 |
SN74S112AD |
|
Unknown
|
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
Historical |
PDF
|
36.99KB |
1 |
SN74S112ADR |
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Texas Instruments
|
SN74S112 - IC S SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SO-16, FF/Latch |
Original |
PDF
|
1.34MB |
19 |
SN74S112ADR |
|
Texas Instruments
|
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET |
Original |
PDF
|
309.88KB |
9 |
SN74S112ADR |
|
Texas Instruments
|
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70 |
Original |
PDF
|
864.89KB |
20 |
SN74S112ADRE4 |
|
Texas Instruments
|
SN74S112 - IC S SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SO-16, FF/Latch |
Original |
PDF
|
1.34MB |
19 |
SN74S112ADRE4 |
|
Texas Instruments
|
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET and CLEAR |
Original |
PDF
|
712.66KB |
17 |
SN74S112ADRE4 |
|
Texas Instruments
|
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70 |
Original |
PDF
|
864.89KB |
20 |
SN74S112ADRG4 |
|
Texas Instruments
|
SN74S112 - IC S SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, GREEN, PLASTIC, SOIC-16, FF/Latch |
Original |
PDF
|
1.34MB |
19 |
SN74S112ADRG4 |
|
Texas Instruments
|
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70 |
Original |
PDF
|
864.89KB |
20 |
|
SN74S112AN |
|
Texas Instruments
|
SN74S112 - Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70 |
Original |
PDF
|
1.34MB |
19 |
SN74S112AN |
|
Texas Instruments
|
Dual J-K Negative-Edge-Triggered Flip-Flop with Preset and Clear |
Original |
PDF
|
309.88KB |
9 |
SN74S112AN |
|
Texas Instruments
|
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70 |
Original |
PDF
|
864.89KB |
20 |
SN74S112AN |
|
Unknown
|
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
Historical |
PDF
|
36.99KB |
1 |
SN74S112AN3 |
|
Texas Instruments
|
SN74S112 - Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70 |
Original |
PDF
|
1.34MB |
19 |
SN74S112AN3 |
|
Texas Instruments
|
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70 |
Original |
PDF
|
864.89KB |
20 |