Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    SNJ54LV165AW Search Results

    SF Impression Pixel

    SNJ54LV165AW Price and Stock

    Texas Instruments SNJ54LV165AW

    Peripheral ICs
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Vyrian SNJ54LV165AW 1,022
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 -
    		Get Quote

    SNJ54LV165AW Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF PDF Size Page count
    SNJ54LV165AW
    		Texas Instruments Parallel-Load 8 Bit Shift Register Original PDF 366.06KB 15
    SNJ54LV165AW
    		Texas Instruments PARALLEL-LOAD 8-BIT SHIFT REGISTERS Original PDF 370.26KB 15

    SNJ54LV165AW Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    A115-A

    Abstract: C101 LV165A SN54LV165A SN74LV165A SN74LV165APWRG3
    Contextual Info: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A A115-A C101 LV165A SN54LV165A SN74LV165A SN74LV165APWRG3 PDF

    Contextual Info: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402L − APRIL 1998 − REVISED MAY 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		SN54LV165A, SN74LV165A SCLS402L 000-V A114-A) A115-A) SN54LV165A PDF

    Contextual Info: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A PDF

    Contextual Info: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A PDF

    Contextual Info: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A PDF

    Contextual Info: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A PDF

    Contextual Info: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode Operation


    Original     		SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A PDF

    Contextual Info: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A PDF

    Contextual Info: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402H – APRIL 1998 – REVISED JANUARY 2003 SN54LV165A . . . J OR W PACKAGE SN74LV165A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 3 14 4 13 5 12 6 11 7 10 8 9 VCC CLK INH D C B A SER QH CLK


    Original     		SN54LV165A, SN74LV165A SCLS402H 000-V A114-A) A115-A) SN54LV165A PDF

    Contextual Info: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D Latch-Up Performance Exceeds 250 mA Per D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D JESD 17


    Original     		SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A PDF

    Contextual Info: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		SN54LV165A, SN74LV165A SCLS402K 000-V A114-A) A115-A) SN54LV165A PDF

    74lv165a

    Abstract: lv165a A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR LV165
    Contextual Info: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		SN54LV165A, SN74LV165A SCLS402K SN54LV165A 74lv165a lv165a A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR LV165 PDF

    A115-A

    Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
    Contextual Info: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		SN54LV165A, SN74LV165A SCLS402K SN54LV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR PDF

    A115-A

    Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
    Contextual Info: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		SN54LV165A, SN74LV165A SCLS402K SN54LV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR PDF

    A115-A

    Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
    Contextual Info: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402I – APRIL 1998 – REVISED JULY 2003 SN54LV165A . . . J OR W PACKAGE SN74LV165A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 3 14 4 13 5 12 6 11 7 10 8 9 VCC CLK INH D C B A SER QH CLK E


    Original     		SN54LV165A, SN74LV165A SCLS402I SN54LV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR PDF

    A115-A

    Abstract: C101 LV165A SN54LV165A SN74LV165A
    Contextual Info: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402D – APRIL 1998 – REVISED JANUARY 2001 D D D D 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22


    Original     		SN54LV165A, SN74LV165A SCLS402D 000-V A114-A) A115-A) SN54LV165A A115-A C101 LV165A SN54LV165A SN74LV165A PDF

    74LV165A

    Contextual Info: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A 74LV165A PDF

    Contextual Info: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A PDF

    A115-A

    Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
    Contextual Info: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		SN54LV165A, SN74LV165A SCLS402K SN54LV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR PDF

    A115-A

    Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
    Contextual Info: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402J − APRIL 1998 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		SN54LV165A, SN74LV165A SCLS402J SN54LV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR PDF

    A115-A

    Abstract: C101 LV165A SN54LV165A SN74LV165A
    Contextual Info: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402D – APRIL 1998 – REVISED JANUARY 2001 D D D D 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22


    Original     		SN54LV165A, SN74LV165A SCLS402D 000-V A114-A) A115-A) SN54LV165A A115-A C101 LV165A SN54LV165A SN74LV165A PDF

    Contextual Info: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402M − APRIL 1998 − REVISED DECEMBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model A114-A


    Original     		SN54LV165A, SN74LV165A SCLS402M 000-V A114-A) A115-A) SN54LV165A PDF

    datasheet lv165a

    Abstract: lV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR 74LV165
    Contextual Info: SN54LV165A, SN74LV165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCLS402H – APRIL 1998 – REVISED JANUARY 2003 SN54LV165A . . . J OR W PACKAGE SN74LV165A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 3 14 4 13 5 12 6 11 7 10 8 9 VCC CLK INH D C B A SER QH CLK


    Original     		SN54LV165A, SN74LV165A SCLS402H SN54LV165A datasheet lv165a lV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR 74LV165 PDF

    A115-A

    Abstract: C101 SN54LV165A SN74LV165A SN74LV165ARGYR
    Contextual Info: SN54LV165A, SN74LV165A PARALLELĆLOAD 8ĆBIT SHIFT REGISTERS SCLS402K − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Support Mixed-Mode Voltage Operation on D All Ports Ioff Supports Partial-Power-Down Mode


    Original     		SN54LV165A, SN74LV165A SCLS402K SN54LV165A A115-A C101 SN54LV165A SN74LV165A SN74LV165ARGYR PDF