TP2522ND Search Results

TA 7139

Abstract: TA 7139 P
Contextual Info: TP2520 TP2522 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information RDS ON (max) VGS(th) (max) ID(ON) (min) TO-243AA* Die† -200V 12Ω -2.4V -0.75A TP2520N8 — -220V 12Ω -2.4V -0.75A TP2522N8 TP2522ND * Same as SOT-89. †

TP2520

Abstract: TP2520N8 TP2522 TP2522N8 TP2522ND voltage drop circuit from 220V to 10V marking TP5C
Contextual Info: TP2520 TP2522 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information RDS ON (max) VGS(th) (max) ID(ON) (min) TO-243AA* Die† -200V 12Ω -2.4V -0.75A TP2520N8 — -220V 12Ω -2.4V -0.75A TP2522N8 TP2522ND * Same as SOT-89. †

marking TP5C

Abstract: TP5C TP2520 TP2520N8 TP2522 TP2522N8 TP2522ND
Contextual Info: TP2520 TP2522 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information RDS ON (max) VGS(th) (max) ID(ON) (min) TO-243AA* Die† -200V 12Ω -2.4V -0.75A TP2520N8 — -220V 12Ω -2.4V -0.75A TP2522N8 TP2522ND * Same as SOT-89. †

Contextual Info: TP2522 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description ► ► ► ► ► ► ► ► This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

Contextual Info: TP2522 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description ► ► ► ► ► ► ► ► This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

TP2522ND

Abstract: TP2522 TP2522N8-G
Contextual Info: TP2522 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description ► ► ► ► ► ► ► This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

A10150

Abstract: TO243AA TP2522 TP2522N8-G TP2522ND A101507
Contextual Info: TP2522 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description ► ► ► ► ► ► ► ► This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

Contextual Info: TP2522 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling

Contextual Info: TP2520 TP2522 Supertex inc. Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Informât on BV dss / R d S ON ^GS(th) I d (ON) Order Num ber / Package b v dgs (max) (max) (min) TO-243AA* Diet -200V 12Í2 -2.4V -0.75A TP2520N8 — -220V 12Í2

SW7 357

Abstract: HV803 ausi die attach CSI 2702 HV208 HV82 38495 VF01 VP03 AF03
Contextual Info: Chapter 19 – Die Specifications DMOS Die Specifications Selector Guide VF01/VF06/VF21/VF25 VF22/LND1/LP07 VF05/VF13/VF26/TN07 VF32/LNE1/LP08 AF03 LR6 LR7 HT04 HV15/HV16/HV18 HV202 HV204/HV217/HV218/HV227/HV228 HV207 HV208 HV209 HV21/HV22 HV31/49 HV34 HV45/HV46