V96SSC Search Results

V96SSC25LP

Contextual Info: ‘ÌOOMEOO 0 0 0 0 3 0 3 ISA V96SSC • * * ▼ / Rev. BO HIGH-INTEGRATION SYSTEM CONTROLLER FOR ¡960 Sx/Jx AND PowerPC 401 Gx PROCESSORS • Direct interface to ¡960Sx/Jx and PPC401Gx processors • High-performance burst DRAM controller • Two-channel fly-by DMA controller

Contextual Info: ÿ y : V96SSC Rev. B1 HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 Sx/Jx AND PowerPC 401 Gx PROCESSORS • Direct interface to i960Sx/Jx and PPC401 Gx processors • High-perform ance burst DRAM controller • Two-channel fly-by DMA controller • Serial com m unications unit

intel DMA controller Unit

Abstract: AV96JA0330420 V350EPC V96SSC V96SSC-33LPB1 A3126
Contextual Info: V96SSC HIGH INTEGRATION SYSTEM CONTROLLER For i960 Jx/Sx and PowerPC 401 Gx Processors Glueless interface between Intel® i960® Jx/Sx series and IBM® PowerPC 401™ Gx processors, DRAM arrays, and peripheral devices Local bus speeds up to 33 MHz High performance burst DRAM

heartbeat counter

Abstract: PPC401GF V960PBC V961PBC V96SSC V96SSC-33LP AD1065 ppc401
Contextual Info: V96SSC Rev. B1 HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960Sx/Jx AND PowerPC 401Gx PROCESSORS • Direct interface to i960Sx/Jx and PPC401Gx processors • High-performance burst DRAM controller • System watchdog and heartbeat timers • 16 general purpose I/O bits

PPC401

Abstract: MAS 10 RCD V3 SEMICONDUCTOR I960SA V96SSC AV9154-04
Contextual Info: Chapter 1 Introduction to the V96SSC The V96SSC High-lntegration System Controller provides many of the common peripheral functions required to build a high-performance ¡960 Sx or ¡960Jx processor based system in one low-cost component. The V96SSC coupled with DRAM, ROM, and one of Intel’s

V96SSC

Abstract: intel i960 EDO dram programmable logic controller timers application heartbeat embedded microprocessors 64 Mb Synchronous DRAM dram controller
Contextual Info: SUPPORT COMPONENTS V3 CORPORATION V96SSC High-Integration Controller • ■ ■ ■ ■ ■ ■ ■ ■ ■ Glueless Interface to Intel’s i960 Sx and i960 Jx Series Processors High-Performance DRAM Controller With DRAM Page Cache Management and EDO Support

Contextual Info: jo t afe « ü V96SSC ‘S’ Core System Controller Advanced Information i960 SA/SB Support Product! Features • • • • • Interfaces directly to the I960 SA/SB Manages Fast Page Mode DRAM Manages Video DRAM VRAM Manages Ramtron Enhanced DRAM (EDRAM)

I960SX

Abstract: V96SSC
Contextual Info: V96SSC Rev B1 HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 Jx/Sx and PowerPC 401Gx PROCESSORS BLOCK DIAGRAM • Glueless interface between Intel’s i960Jx and i960Sx series processors, DRAM arrays, and peripheral devices Fast time-to-market • Support for boot PROM devices

Contextual Info: Chapter 1 Introduction to the V96SSC The V96SSC High-lntegration System Controller provides many of the common peripheral functions required to build a high-perform ance ¡960 Sx or ¡960Jx processor based system in one low-cost component. The V96SSC coupled with DRAM, ROM, and one of Intel’s

AV96JA0330420

Abstract: V350EPC V350EPC-33LPA1 V350EPC-40LPA1 V380SDC V96BMC V96SSC PCI bridge
Contextual Info: V350EPC ENHANCED PCI BRIDGE CONTROLLER For 32-bit Multiplexed Address/Data Bus Fully compliant with PCI Local Bus Specification, Revision 2.1 Configurable for system master, PCI master, or PCI target operation 32-bit, 33 MHz PCI bus interface Direct interface to Intel i960®

Contextual Info: V960PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR ¡960 Sx PROCESSORS • Glueless interface between Intel ¡960Sx, processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation • Up to 1 Kbyte burst access support on both local

Contextual Info: V961PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR MUTLTELEXED A/D PROCESSORS • Dual bi-directional address space remapping • Glueless interface between Intel i960Jx, IBM PPC401Gx, processors and PCI bus • On-the-fly byte order endian conversion • Fully compliant with PCI 2.1 specification

Contextual Info: ^004200 □□□□102 MST • V961PBC •" V Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Jx AND PowerPC 401 Gx PROCESSORS " • Glueless interface between ¡960Jx, PPC401 Gx processors and the PCI bus • Large, 576-byte FIFOs using V3's unique D y n a m ic B a n d w id t h A l l o c a t i o n ™ architecture

Contextual Info: T 0 Q 4 E D 0 D D D O H b b 212 V292BMC Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER :.V “ FOR Am29030/40 PROCESSORS • Pin/Software compatible with earlier V292BMC. • Integrated Page Cache Management. • Direct interfaces to Am29030/40 processors.

V363EPC

Abstract: V363EPC-50LPA0 29030 V380SDC V96BMC V96SSC
Contextual Info: V363EPC ENHANCED PCI BRIDGE CONTROLLER For 32-bit Multiplexed/Demultiplexed Address/Data Bus Fully compliant with PCI Local Bus Specification, Revision 2.1 Configurable for system master, PCI master, or PCI target operation 32-bit, 33 MHz PCI bus interface

160-Pin Flat Package pci bridge

Contextual Info: 936&5HY$ PCI Bus Target Interface Data Sheet Revision 1.1 V3 Semiconductor Corp V3 Semiconductor makes no warranties for the use of its products. V3 does not assume any liability for errors which may appear in this document, however, we will attempt to notify customers of such errors.

Contextual Info: • TD042DD 0000132 V292PBC 117 Rev. B1 LOCAL BUS TO PCI BRIDGE FOR Am29K PROCESSORS '« IC O * ” ’ • Glueless interface between Am29030/40 processors and the PCI bus • Large, 576-byte FIFOs using V3’s unique D y n a m ic B a n d w id t h A l l o c a t i o n ™ architecture

PJ3N

Contextual Info: . . y lf • * ▼ • =1004200 0 0 0 0 0 2 1 V96DPC f « 450 ■ Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Cx/Hx/Jx/Sx AND PowerPC 40lGx PROCESSORS • Glueless interface between i960Sx/Jx/Cx/Hx, PPC401 Gx processors and two PCI buses • On-the-fly byte order endian conversion

AD14

Abstract: AD30 PPC401GF V292PBC V961PBC V961PBC-33 V961PBC-40 V96BMC V96SSC
Contextual Info: V961PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface between Intel i960Jx, IBM PPC401Gx, processors and PCI bus • Dual bi-directional address space remapping • On-the-fly byte order endian conversion • Fully compliant with PCI 2.1 specification

Contextual Info: Chapter 1 Introduction In a very short period of tim e the PCI bus standard has moved beyond the PC to become the most w idely accepted high-perform ance bus standard for embedded applications. As a leader in providing chipset solutions for high-end embedded applications, V3 Sem iconductor

Contextual Info: - V 9 6 1 P B C Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Jx AND PowerPC 401 Gx PROCESSORS yi '« IC O * ’ • Glueless interface between i960Jx, PPC401Gx processors and the PCI bus • Large, 576-byte FIFOs using V3’s unique D y n a m ic B a n d w id t h A l l o c a t io n ™ architecture

V360EPC-50LPA1

Abstract: v360epc-50lp V360EPC-33LP 29030 V360EPC V360EPC-33LPA1 V380SDC V96BMC V96SSC SPACE BRIDGE SEMICONDUCTOR
Contextual Info: V360EPC ENHANCED PCI BRIDGE CONTROLLER For 32-bit De-Multiplexed Address/Data Bus Fully compliant with PCI Local Bus Specification, Revision 2.1 Configurable for system master, PCI master, or PCI target operation 32-bit, 33 MHz PCI bus interface Direct interface to Intel i960®

Contextual Info: V961PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR MUTLTELEXED A/D PROCESSORS • Glueless interface between Intel ¡960Jx, IBM PPC401Gx, processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation

Contextual Info: •iOONSna 0 0 0 0 0 4 7 V960PBC V 313 Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Sx PROCESSORS “ • Glueless interface between ¡960Sx processors and the PCI bus • Large, 576-byte FIFOs using V3’s unique D y n a m ic B a n d w id t h A l l o c a t i o n architecture