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    XC17V00 Search Results

    XC17V00 Datasheets (3)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    XC17V00 Xilinx Original PDF
    XC17V00 Series Xilinx XC17V00 Series Configuration PROMs Original PDF
    XC17V00-SERIES-CONFIGURATION-PROMS Xilinx XC17V00 Series Configuration PROMs Original PDF

    XC17V00 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    SPARTAN XC2S50

    Abstract: 18V02 xilinx 8 pin dip Xilinx XC2V500 XILINX SPARTAN XC2S50 18V512 18V00 SPARTAN 6 Configuration FPGA Virtex 6 pin configuration 17S00A
    Text: Xilinx Configuration PROMs XC18V00, XC17V00, XC17S00 FPGA Configuration PROMs 180V00 PROM Family Based on the Xilinx state-of-the-art ISP PROM architecture and manu- • PROM-triggered FPGA reconfiguration via JTAG factured on an advanced 0.35m • Up to 264 MHz configuration speed


    Original     		PDF XC18V00, XC17V00, XC17S00 180V00 18V00 256Kb 44-pin 20-pin SPARTAN XC2S50 18V02 xilinx 8 pin dip Xilinx XC2V500 XILINX SPARTAN XC2S50 18V512 SPARTAN 6 Configuration FPGA Virtex 6 pin configuration 17S00A

    XCR3000XL

    Abstract: vqfp 44 HW-137-DIP8 HQFP HW-133-BG256 HW-136-VQ100 vqfp44 HW-137-PC44/VQ44 HW-136-CS144 xc17v00
    Text: HW-130 Programmer R DS019 v1.8 May 25, 2007 Product Specification Device and Package Support Programmer Functional Specifications • XC1700/XC17S00/XL Serial PROMs • Device programming, erasing, and verification • XC17V00/XC17S00A Serial PROMs • CPLD security control


    Original     		PDF HW-130 DS019 XC1700/XC17S00/XL XC17V00/XC17S00A XC18V00 XC9500/XL/XV XCR3000XL XC7200/7300 XC9500/XL XC1800 vqfp 44 HW-137-DIP8 HQFP HW-133-BG256 HW-136-VQ100 vqfp44 HW-137-PC44/VQ44 HW-136-CS144 xc17v00

    SPARTAN-3 XC3S400

    Abstract: XC17V00 SPARTAN-3 XC3S1000 XC17V16 Series xc3s400 pinout xilinx MARKING CODE PC44 SO20 VQ44 XC3S400 FPGAs
    Text: XC17V00 Series Configuration PROMs DRAFT R DS073 (v1.12) July 25, 2003 8 Features • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices • • Simple interface to the FPGA Cascadable for storing longer or multiple bitstreams


    Original     		PDF XC17V00 DS073 XC17V16 XC17V08 XC17V04, XC17V02, XC17V01 XC17V08. SPARTAN-3 XC3S400 SPARTAN-3 XC3S1000 XC17V16 Series xc3s400 pinout xilinx MARKING CODE PC44 SO20 VQ44 XC3S400 FPGAs

    XCN07010

    Abstract: XC17V00 DS07-3 XC17V04VQ44I PC44 SO20 VQ44 xilinx XC3S200
    Text: R DS073 v1.12 November 13, 2008 XC17V00 Series Configuration PROMs Product Specification 8 Features • Available in compact plastic packages: VQ44, PC44, PC20, VO8, and SO20(1) • Programming support by leading programmer manufacturers Cascadable for storing longer or multiple bitstreams


    Original     		PDF DS073 XC17V00 XCN07010 DS07-3 XC17V04VQ44I PC44 SO20 VQ44 xilinx XC3S200

    XC17V00

    Abstract: xilinx 8 pin dip
    Text: New Products PROMs New High-Density Virtex PROMs and Cost-Effective Spartan-II PROMs Xilinx announces the addition of the XC17V00 and XC17S00A families to its existing line of onetime programmable OTP PROMs. 30 by Theresa Vu Product Marketing Engineer, Xilinx Inc.


    Original     		PDF XC17V00 XC17S00A xilinx 8 pin dip

    XC17V00

    Abstract: No abstract text available
    Text: XC17V00 Series Configuration PROMs R DS073 v1.6 February 27, 2002 8 Features Advance Product Specification • Available in compact plastic packages: VQ44, PC44, PC20, VO8, and SO20 • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx


    Original     		PDF XC17V00 DS073 XC17V16 XC17V08 XC17V08, SCV405E,

    XC17V00

    Abstract: xilinx SO20 MARKING CODE PC44 SO20 VQ44 SelectMAP
    Text: R DS073 v1.11 June 7, 2007 XC17V00 Series Configuration PROMs Product Specification 8 Features • Available in compact plastic packages: VQ44, PC44, PC20, VO8, and SO20 • Programming support by leading programmer manufacturers. Cascadable for storing longer or multiple bitstreams


    Original     		PDF DS073 XC17V00 XC3S50 XC17V04, XC17V02, XC17V01, XC17V16 XC17V08, xilinx SO20 MARKING CODE PC44 SO20 VQ44 SelectMAP

    SelectMAP

    Abstract: No abstract text available
    Text: XC17V00 Series Configuration PROMs R DS073 v1.8 July 29, 2002 8 Features Advance Product Specification • Available in compact plastic packages: VQ44, PC44, PC20, VO8, and SO20 • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx


    Original     		PDF XC17V00 DS073 XC17V16 XC17V08 SCV405E, SelectMAP

    Untitled

    Abstract: No abstract text available
    Text: XC17V00 Series Configuration PROM R DS073 v1.2 November 16, 2000 8 Advance Product Specification Features Description • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices • Simple interface to the FPGA; configurable to use a


    Original     		PDF XC17V00 DS073 44-pin 20-pin XC17V16 XC17V08, XC17V08

    17V16

    Abstract: XC17V04PC44I XC17V04VQ44I XC17V16 Series xilinx MARKING CODE PC44 SO20 VQ44 XC17V00 17V01
    Text: XC17V00 Series Configuration PROM R DS073 v1.0 July 26, 2000 8 Advance Product Specification Features Description • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices • Simple interface to the FPGA; configurable to use a


    Original     		PDF XC17V00 DS073 17V16 17V16 17V08 17V04 17V02 17V01 44-pin XC17V04PC44I XC17V04VQ44I XC17V16 Series xilinx MARKING CODE PC44 SO20 VQ44 17V01

    Untitled

    Abstract: No abstract text available
    Text: — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — R DS073 v2.0 April 7, 2014 XC17V00 Series Configuration PROMs Product Specification 8 Features • Available in compact plastic packages: VQ44, PC44, PC20, VO8, and SO20(1) • Programming support by leading programmer


    Original     		PDF DS073 XC17V00

    44-PIN PLASTIC QUAD FLAT PACKAGE

    Abstract: xilinx MARKING CODE xilinx SO20 MARKING CODE XC17V00
    Text: XC17V00 Series Configuration PROM R DS073 v1.4 April 4, 2001 8 Advance Product Specification Features Description • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices • Simple interface to the FPGA


    Original     		PDF XC17V00 DS073 XC17V16 XC17V08 20-pin XC17V08, XC17V08 44-PIN PLASTIC QUAD FLAT PACKAGE xilinx MARKING CODE xilinx SO20 MARKING CODE

    XC17V00

    Abstract: XC17V08 Series PC44 SO20 VQ44
    Text: XC17V00 Series Configuration PROMs R DS073 v1.10 April 14, 2002 8 Features Preliminary Product Specification • Available in compact plastic packages: VQ44, PC44, PC20, VO8, and SO20 • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx


    Original     		PDF XC17V00 DS073 XC17Vs XC17V04, XC17V02, XC17V01 XC17V16 XC17V08. XC17V08 Series PC44 SO20 VQ44

    XC17V00 Series

    Abstract: XC17V04VQ44I XC2V1000-4 xcv300 Date Marking
    Text: XC17V00 Series Configuration PROMs R DS073 v1.7 June 14, 2002 8 Features Advance Product Specification • Available in compact plastic packages: VQ44, PC44, PC20, VO8, and SO20 • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx


    Original     		PDF XC17V00 DS073 XC17V16 XC17V08 SCV405E, XC17V00 Series XC17V04VQ44I XC2V1000-4 xcv300 Date Marking

    datasheet transistor said horizontal tt 2222

    Abstract: interface of rs232 to UART in VHDL xc9500 80C31 instruction set apple ipad schematic drawing 8 bit alu in vhdl mini project report apple ipad 2 circuit schematic apple ipad Apple iPad 2 panasonic inverter dv 700 manual TT 2222 Horizontal Output Transistor pins out
    Text: Virtex-II Platform FPGA User Guide UG002 v2.2 5 November 2007 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		PDF UG002 datasheet transistor said horizontal tt 2222 interface of rs232 to UART in VHDL xc9500 80C31 instruction set apple ipad schematic drawing 8 bit alu in vhdl mini project report apple ipad 2 circuit schematic apple ipad Apple iPad 2 panasonic inverter dv 700 manual TT 2222 Horizontal Output Transistor pins out

    XC17S200APD8C

    Abstract: XC17S00A XC2S100 XC2S100E XC2S15 XC2S150 XC2S200 XC2S30 XC2S50 XC2S50E
    Text: Spartan-II/Spartan-IIE Family OTP Configuration PROMs XC17S00A R DS078 (v1.10) June 25, 2007 Product Specification 5 Features • Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan -II/Spartan-IIE FPGA devices


    Original     		PDF XC17S00A) DS078 20-year 20-pin 44-pin XC17S150APD8C XC17S15AVO8C XC17S50APDG8C XC17S150AVO8C XC17S15AVOG8C XC17S200APD8C XC17S00A XC2S100 XC2S100E XC2S15 XC2S150 XC2S200 XC2S30 XC2S50 XC2S50E

    PC44

    Abstract: SO20 VQ44 XC17V00 XC18V00 XC2VP20 XC2VP30 XC2VP40
    Text: XC18V00 Series In-System Programmable Configuration PROMs R DS026 v5.0 April 5, 2004 Features • Product Specification • Dual configuration modes - Serial Slow/Fast configuration (up to 33 MHz) - Parallel (up to 264 Mb/s at 33 MHz) In-system programmable 3.3V PROMs for


    Original     		PDF XC18V00 DS026 XC18V04 XC18V02, XC18V01 XC18V512, PC44 SO20 VQ44 XC17V00 XC2VP20 XC2VP30 XC2VP40

    xc18v02 Date Marking

    Abstract: XC18V04 XC18V02 XC18V128 XC18V04VQ44C xilinx SO20 MARKING CODE XC18V01VQ44C XC18V01pc20c marking XC18V01SO20C XC18V00
    Text: XC18V00 Series In-System Programmable Configuration PROMs R DS026 v3.10 April 17, 2003 Features • Product Specification • Dual configuration modes - Serial Slow/Fast configuration (up to 33 MHz) - Parallel (up to 264 Mb/s at 33 MHz) In-system programmable 3.3V PROMs for


    Original     		PDF XC18V00 DS026 XC2S400E XC2S600E xc18v02 Date Marking XC18V04 XC18V02 XC18V128 XC18V04VQ44C xilinx SO20 MARKING CODE XC18V01VQ44C XC18V01pc20c marking XC18V01SO20C

    xilinx MARKING CODE XC4000

    Abstract: XC18V01SO20C 18V512 XC18V00
    Text: XC18V00 Series of In-System Programmable Configuration PROMs R DS026 v2.7 April 4, 2001 5 Product Specification Features Description • Xilinx introduces the XC18V00 series of in-system programmable configuration PROMs. Initial devices in this 3.3V family are a 4-megabit, a 2-megabit, a 1-megabit, a 512-Kbit,


    Original     		PDF XC18V00 DS026 512-Kbit, 256-Kbit XC18V01, XC18V512, XC18V256 xilinx MARKING CODE XC4000 XC18V01SO20C 18V512

    XC18V01SO20C

    Abstract: 18V256 XC18V00 XC18V04 XC2S100 XC18V04VQ44I XC18V01PC20I
    Text: XC18V00 Series of In-System Programmable Configuration PROMs R DS026 v3.5 June 14, 2002 Features • Product Specification • Dual configuration modes - Serial Slow/Fast configuration (up to 33 MHz) - Parallel (up to 264 Mb/s at 33 MHz) In-system programmable 3.3V PROMs for


    Original     		PDF XC18V00 DS026 XC18V01SO20C 18V256 XC18V04 XC2S100 XC18V04VQ44I XC18V01PC20I

    48-pin TSOP (I) flash memory

    Abstract: am29lv Am29LV320D application mpm h1 a20 g6 amd CS144 XCV50E AMD 2m flash memory FPGA Virtex 6 pin configuration XC17V00
    Text: ds088_1_1.fm Page 1 Wednesday, June 19, 2002 5:31 PM R DS088 v1.2 June 7, 2002 System ACE SC Solution Advance Product Specification Summary • • • • • • • System-level, high-capacity, pre-configured solution for Virtex Series FPGAs, Virtex-II Series Platform


    Original     		PDF DS088 XCV50E-6CS144 Am29LV160D XCCACEM16-CS144-AM Am29LV320D XCCACEM32-CS144-AM Am29LV641D XCCACEM64-CS144-AM 48-pin TSOP (I) flash memory am29lv Am29LV320D application mpm h1 a20 g6 amd CS144 XCV50E AMD 2m flash memory FPGA Virtex 6 pin configuration XC17V00

    18v04

    Abstract: XC17v X07905 xilinx jtag cable XCV2VP50 17V01 18V00 Virtex-II Pro Prototype Platform User Guide
    Text: R Chapter 3 Configuration Summary This chapter covers the following topics: • • • • • • • • • • Introduction Configuration Solutions Master Serial Programming Mode Slave Serial Programming Mode Master SelectMAP Programming Mode Slave SelectMAP Programming Mode


    Original     		PDF RS232 98/2000/NT UG012 18v04 XC17v X07905 xilinx jtag cable XCV2VP50 17V01 18V00 Virtex-II Pro Prototype Platform User Guide

    apple ipad schematic drawing

    Abstract: xpower inverter 3000 plus apple ipad 8 bit alu in vhdl mini project report apple ipad 2 circuit schematic 8051 code assembler for data encryption standard XC2VP2-FG256 vhdl code for FFT 32 point Rayovac 357 apple ipad battery charge controller
    Text: Virtex-II Pro and Virtex-II Pro X FPGA User Guide UG012 v4.2 5 November 2007 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		PDF UG012 apple ipad schematic drawing xpower inverter 3000 plus apple ipad 8 bit alu in vhdl mini project report apple ipad 2 circuit schematic 8051 code assembler for data encryption standard XC2VP2-FG256 vhdl code for FFT 32 point Rayovac 357 apple ipad battery charge controller

    HW-137-DIP8

    Abstract: soic-20 XCN07022 XCR3000XL HW-133-PC44 HW-130-J HW-137-PC44/VQ44 XC18V00 XC7200 HW-130
    Text: R HW-130 Programmer DS019 v1.9 February 8, 2008 Product Specification This product is undergoing discontinuance. Please refer to XCN07022, Product Discontinuation Notice, for more information on last-time purchases and replacement products. Device and Package Support


    Original     		PDF HW-130 DS019 XCN07022, XC1700/XC17S00/XL XC17V00/XC17S00A XC18V00 XC9500/XL/XV XCR3000XL HW-137-DIP8 soic-20 XCN07022 HW-133-PC44 HW-130-J HW-137-PC44/VQ44 XC7200