Untitled
Abstract: No abstract text available
Text: áç XRT71D03 PRELIMINARY 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER DECEMBER 2000 REV. P1.0.2 GENERAL DESCRIPTION The XRT71D03 is a three channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristics requirements specified in the ETSI TBR-24,
|
Original
|
XRT71D03
XRT71D03
TBR-24,
GR-499
GR-253
755oration
|
PDF
|
GR-253
Abstract: TBR24 XRT71D03 XRT71D04
Text: áç XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER APRIL 2001 REV. 1.1.1 GENERAL DESCRIPTION The XRT71D03 is a three channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristics requirements specified in the ETSI TBR-24,
|
Original
|
XRT71D03
XRT71D03
TBR-24,
GR-499
GR-253
TBR24
TBR24
XRT71D04
|
PDF
|
Untitled
Abstract: No abstract text available
Text: DATA SHEET Communications DS3/E3 Jitter Attenuator XRT71D03 Three Channel DS3/E3/STS-1 Jitter Attenuator, STS-1 to DS3 Desynchronizer Features • Supports DS3/E3/STS-1 rates • Each channel can operate at different data rates • Selectable buffer size 16- or 32-bit
|
Original
|
XRT71D03
32-bit)
64-pin
XRT71D03)
80-pin
XRT71D04)
XRT71D00,
XRT71D03,
XRT71D04
TBR-24
|
PDF
|
Untitled
Abstract: No abstract text available
Text: DATA SHEET Communications XRT71D04 DS3/E3 Jitter Attenuator Features • Supports DS3/E3/STS-1 rates • Each channel can operate at different data rates • Selectable buffer size 16- or 32-bit • Available in either a 64-pin (XRT71D03), or a 80-pin (XRT71D04) TQFP package
|
Original
|
XRT71D04
32-bit)
64-pin
XRT71D03)
80-pin
XRT71D04)
XRT71D00,
XRT71D03
TBR-24
|
PDF
|
Untitled
Abstract: No abstract text available
Text: áç XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER APRIL 2001 REV. 1.1.0 GENERAL DESCRIPTION The XRT71D03 is a three channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristics requirements specified in the ETSI TBR-24,
|
Original
|
XRT71D03
XRT71D03
TBR-24,
GR-499
GR-253
TBR24
|
PDF
|
GR-253
Abstract: TBR24 XRT71D03 XRT71D03IV XRT71D04 IC 2576 5.0v
Text: áç XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER SEPTEMBER 2001 REV. 1.1.2 GENERAL DESCRIPTION The XRT71D03 is a three channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristics requirements specified in the ETSI TBR-24,
|
Original
|
XRT71D03
XRT71D03
TBR-24,
GR-499
GR-253
TBR24
TBR24
XRT71D03IV
XRT71D04
IC 2576 5.0v
|
PDF
|
ANSI T1.105.03B 1997
Abstract: No abstract text available
Text: DATA SHEET Communications XRT71D03 DS3/E3 Jitter Attenuator Features • Supports DS3/E3/STS-1 rates • Each channel can operate at different data rates • Selectable buffer size 16- or 32-bit • Available in either a 64-pin (XRT71D03), or a 80-pin (XRT71D04) TQFP package
|
Original
|
XRT71D03
32-bit)
64-pin
XRT71D03)
80-pin
XRT71D04)
XRT71D00,
XRT71D03,
XRT71D04
TBR-24
ANSI T1.105.03B 1997
|
PDF
|
relay finder t29
Abstract: No abstract text available
Text: áç XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR SEPTEMBER 2001 REV. 1.2.0 GENERAL DESCRIPTION The XRT71D03 is a three channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristics requirements specified in the ETSI TBR-24, Bellcore GR-499 and GR-253 standards.
|
Original
|
XRT71D03
XRT71D03
TBR-24,
GR-499
GR-253
GR-235-CORE,
GR499-CORE
relay finder t29
|
PDF
|
Untitled
Abstract: No abstract text available
Text: áç XRT71D03 PRELIMINARY 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER SEPTEMBER 2000 REV. P1.0.1 GENERAL DESCRIPTION The XRT71D03 is a three channel, single chip Jitter Attenuator, that meets the Jitter requirements specified in the ETSI TBR-24, Bellcore GR-499 and GR253 standards.
|
Original
|
XRT71D03
XRT71D03
TBR-24,
GR-499
GR253
GR-253
GR-499-CORE
|
PDF
|
IC 2576 5.0v
Abstract: GR-253 TBR24 XRT71D03 XRT71D03IV XRT71D04 71d0
Text: áç XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR SEPTEMBER 2001 REV. 1.2.0 GENERAL DESCRIPTION The XRT71D03 is a three channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristics requirements specified in the ETSI TBR-24, Bellcore GR-499 and GR-253 standards.
|
Original
|
XRT71D03
XRT71D03
TBR-24,
GR-499
GR-253
TBR24
IC 2576 5.0v
TBR24
XRT71D03IV
XRT71D04
71d0
|
PDF
|
Untitled
Abstract: No abstract text available
Text: xr PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - CC/HDLC ARCHITECTURAL DESCRIPTION NOVEMBER 2005 GENERAL DESCRIPTION The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter
|
Original
|
XRT79L71
XRT79L71
|
PDF
|
Untitled
Abstract: No abstract text available
Text: áç XRT73L03 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT JULY 2001 REV. 1.2.0 GENERAL DESCRIPTION The XRT73L03, 3-Channel, DS3/E3/STS-1 Line Interface Unit consists of three independent line transmitters and receivers integrated on a single chip designed for DS3, E3 or SONET STS-1 applications.
|
Original
|
XRT73L03
XRT73L03,
XRT73L03
|
PDF
|
Untitled
Abstract: No abstract text available
Text: XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.4 GENERAL DESCRIPTION The XRT73LC03A, 3-Channel, DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L03A and consists of three independent line transmitters and receivers integrated on a single chip
|
Original
|
XRT73LC03A
XRT73LC03A,
XRT73L03A
XRT73LC03A
|
PDF
|
r4363
Abstract: CP Clare RELAY dmo 465 IC 404
Text: áç XRT72L53 PRELIMINARY THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER JANUARY 2001 REV. P1.1.6 GENERAL DESCRIPTION The XRT72L53, 3 Channel DS3/E3 Framer IC is designed to accept User Data from the Terminal Equipment and insert this data into the Payload bit-fields
|
Original
|
XRT72L53
XRT72L53,
XRT72L53
DS3-M13,
r4363
CP Clare RELAY
dmo 465
IC 404
|
PDF
|
|
|
dmo 365 r
Abstract: datasheet relay NAIS 5v 5 pin NAIS Relay 5v bi directional dc motor speed controller NAIS 210 NAIS 210 RELAY 5v relay nais 5 pin data sheet DS3-M13 sha t90 T79 code marking
Text: áç XRT72L53 PRELIMINARY THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER FEBRUARY 2001 REV. P1.1.7 GENERAL DESCRIPTION The XRT72L53, 3 Channel DS3/E3 Framer IC is designed to accept User Data from the Terminal Equipment and insert this data into the Payload bit-fields
|
Original
|
XRT72L53
XRT72L53,
XRT72L53
DS3-M13,
dmo 365 r
datasheet relay NAIS 5v 5 pin
NAIS Relay 5v
bi directional dc motor speed controller
NAIS 210
NAIS 210 RELAY
5v relay nais 5 pin data sheet
DS3-M13
sha t90
T79 code marking
|
PDF
|
EXAR XR2209
Abstract: XR16C2850 XR68C681 XR88C192 ST16C650A
Text: ABOUT EXAR I PRODUCTS I INDEX I SALES INFO I INFORMATION REQUEST I SEARCH I HELP I Exar Products Alphanumeric Index To access product information and data sheets, click on the part number below. ST16C1450 ST16C1451 ST16C1550 ST16C1551 ST16C2450 ST16C2550 ST16C2552
|
Original
|
ST16C1450
ST16C1451
ST16C1550
ST16C1551
ST16C2450
ST16C2550
ST16C2552
ST16C450
ST16C452-PS
ST16C454
EXAR XR2209
XR16C2850
XR68C681
XR88C192
ST16C650A
|
PDF
|
XR2206 application notes
Abstract: pin diagram of ic xr2206 IC XR2206 XR2206 XR2206 pin details for function generator XR2206 monolithic function generator xr2206 circuit peb1756ae fsk modulation and demodulation using Xr2206 MXP2
Text: Communications OTN Multi-Service OTN Muxponder/Mapper Ethernet Transport Ethernet over PDH Ethernet over SONET/SDH PDH over SONET/SDH Port Expanders SONET/SDH Multi-Ch/Multi-Rate Framer+Serdes Mappers + Framers Transceivers/CDR PDH E1 LIUs T1/E1/J1 LIUs BITS Solutions
|
Original
|
acqui010
350MHz
XRT8020
XRT85L61
QFN-16
TSSOP-28
XR2206 application notes
pin diagram of ic xr2206
IC XR2206
XR2206
XR2206 pin details for function generator
XR2206 monolithic function generator
xr2206 circuit
peb1756ae
fsk modulation and demodulation using Xr2206
MXP2
|
PDF
|
Untitled
Abstract: No abstract text available
Text: XRT73L03B 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT JULY 2003 REV. 1.0.0 GENERAL DESCRIPTION The XRT73L03B, 3-Channel, DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L03A and consists of three independent line transmitters and receivers integrated on a single chip
|
Original
|
XRT73L03B
XRT73L03B,
XRT73L03A
XRT73L03B
|
PDF
|
dmo 465
Abstract: iC 458 datasheet relay NAIS 5v 5 pin M25-A dmo 365 dmo 365 r NAIS 210 RELAY NAIS Relay 5v DS3-M13 XRT72L56
Text: áç XRT72L56 PRELIMINARY SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER JANUARY 2001 REV. P1.1.2 GENERAL DESCRIPTION The Microprocessor Interface is used to configure the Framer in different operating modes and monitor the performance of the Framer. The XRT72L56, 6 Channel DS3/E3 Framer is designed to accept “User Data” from the Terminal
|
Original
|
XRT72L56
XRT72L56,
XRT72L56
dmo 465
iC 458
datasheet relay NAIS 5v 5 pin
M25-A
dmo 365
dmo 365 r
NAIS 210 RELAY
NAIS Relay 5v
DS3-M13
|
PDF
|
NAIS 210 RELAY
Abstract: ic 393 k 4213 0X13 DS3-M13 XRT72L52
Text: áç XRT72L52 PRELIMINARY TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER JANUARY 2001 REV. P1.1.2 GENERAL DESCRIPTION The XRT72L52, 2 Channel DS3/E3 Framer IC is designed to accept “User Data” from the Terminal Equipment and insert this data into the “payload” bitfields within an “outbound” DS3/E3 Data Stream. Further, the Framer IC is also designed to receive an “inbound” DS3/E3 Data Stream from the Remote Terminal Equipment and extract out the “User Data”.
|
Original
|
XRT72L52
XRT72L52,
XRT72L52
DS3-M13,
NAIS 210 RELAY
ic 393
k 4213
0X13
DS3-M13
|
PDF
|
Untitled
Abstract: No abstract text available
Text: I ABOUT EXAR I PRODUCTS I INDEX I SALES INFORMATION I INFORMATION REQUEST I SEARCH I HELP I DS3/E3 Product Selector Guide DS3/E3 Products DS3/E3 Line Interfaces Part No. #of Channels Data Rates Clock Recovery Temp Range Operating Power Supply Max Current Package s
|
Original
|
111mA
106mA
133mA
XRT7295
XRT7295E
XRT7296
XRT7298
XRT7300
XRT73L00
|
PDF
|
Untitled
Abstract: No abstract text available
Text: DATA SHEET Communications XRT75L00 Single-Chip Line Interface Unit LIU With Jitter Attenuator (JA) for DS3/E3 Environments Features: Receiver: • On-Chip Clock and Data Recovery Circuit for High-Input Jitter Tolerance • On-Chip B3ZS/HDB3 Encoder/Decoder Can be Disabled or Enabled
|
Original
|
XRT75L00
XRT75L00D
GR-499
GR-253
TBR-24,
|
PDF
|
DMO 565 R
Abstract: No abstract text available
Text: xr PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - ATM ARCHITECTURAL DESCRIPTION NOVEMBER 2005 GENERAL DESCRIPTION The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter
|
Original
|
XRT79L71
XRT79L71
DMO 565 R
|
PDF
|
Rx1302
Abstract: r4363 dmo 265
Text: áç XRT72L50 PRELIMINARY SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER JANUARY 2001 REV. P1.1.2 GENERAL DESCRIPTION The XRT72L50, single Channel DS3/E3 Framer IC is designed to accept “User Data” from the Terminal Equipment and insert this data into the “payload” bitfields within an “outbound” DS3/E3 Data Stream. Further, the Framer IC is also designed to receive an “inbound” DS3/E3 Data Stream from the Remote Terminal Equipment and extract out the “User Data”.
|
Original
|
XRT72L50
XRT72L50,
XRT72L50
DS3-M13,
Rx1302
r4363
dmo 265
|
PDF
|
