XRT7245 Search Results

8032 Intel Microprocessor data Sheet

Abstract: atm header error checking ATM machine using microcontroller dmo 265 NAIS 210 T7296 3-bit comparator circuit receives two 3-bit 8052 microcontroller Intel LOG RX 2 1018 IC ordinary calculator programming
Contextual Info: áç XRT7245 PRELIMINARY DS3 UNI FOR ATM DECEMBER 1999 REV. 1.03 GENERAL DESCRIPTION • Contains on-chip 16 cell FIFO configurable in The XRT7245 DS3 ATM User Network Interface (UNI device is designed to provide the ATM Physical Layer (Physical Medium Dependent and Transmission Convergence sub-layers) interface for the public

8052 microcontroller Intel

Abstract: GR-499-CORE XRT7295 XRT7296 XR-T7296 XRT7300 flowchart of LCD interface with 8051 fc22825
Contextual Info: áç XRT7245 PRELIMINARY DS3 UNI FOR ATM DECEMBER 1999 REV. 1.03 GENERAL DESCRIPTION • Contains on-chip 16 cell FIFO configurable in The XRT7245 DS3 ATM User Network Interface (UNI device is designed to provide the ATM Physical Layer (Physical Medium Dependent and Transmission Convergence sub-layers) interface for the public

Contextual Info: DATA SHEET Communications ATM XRT7245 DS3 UNI User Network Interface IC for ATM The XR-T7245 DS3 ATM User Network Interface (UNI) device is designed to provide the ATM Physical Layer (Physical Medium Dependent and Transmission Convergence sub-layers) interface for the public and private networks at DS3 rates. This device

74222 fifo

Abstract: NAIS 210 GR-499-CORE XRT7295 XRT7296 XRT7300 S/74222 fifo
Contextual Info: áç XRT7245 PRELIMINARY DS3 UNI FOR ATM DECEMBER 1999 REV. 1.03 GENERAL DESCRIPTION • Contains on-chip 16 cell FIFO configurable in The XRT7245 DS3 ATM User Network Interface (UNI device is designed to provide the ATM Physical Layer (Physical Medium Dependent and Transmission Convergence sub-layers) interface for the public

Contextual Info: Preliminary 7P E X A R XR-T7245 DS3 UNI User Network Interface 1C for ATM .the analog plus company TM June 1997-3 FEATURES APPLICATIONS Compliant with UTOPIA Level 2 Interface Specification ATM Switches ATM Routers and Bridges Supports 8 or 16 Bit UTOPIA Bus Operating at

GR-253-CORE

Abstract: GR-499-CORE PE-65966 PE-65967 PE-68629 T3001 XRT7300 XRT7300IV
Contextual Info: XRT7300 JBTEXAR E3/DS3/STS-1 Line Interface Unit Septem ber 1999-2 FEATURES • Single-chip Transmit and Receive Line Interface IC for E3 34.368Mbps , DS3 (44.736Mbps) and SONET STS-1 (51,84Mbps) Applications Transmit Interface Characteristics • Accepts Either Single Rail or Dual Rail Data

EXAR XR2209

Abstract: XR16C2850 XR68C681 XR88C192 ST16C650A
Contextual Info: ABOUT EXAR I PRODUCTS I INDEX I SALES INFO I INFORMATION REQUEST I SEARCH I HELP I Exar Products Alphanumeric Index To access product information and data sheets, click on the part number below. ST16C1450 ST16C1451 ST16C1550 ST16C1551 ST16C2450 ST16C2550 ST16C2552

Contextual Info: DATA SHEET Communications T3/STS-1/E3 XRT7300 DS3/E3/STS-1 Line Interface Unit Exar's XRT7300 DS3/E3/STS-1 transceiver is an integrated solution which combines and enhances the present XRT7295/XRT7298 two-chip solution. The device contains both the receiver and transmitter to support the data rates at DS3 44.736Mbps , E3 (34.368Mbps)

Contextual Info: Preliminary XR-T7245 «/ DS3 UNI User Network Interface 1C for ATM December 1997-1 FEATURES APPLICATIONS • Compliant with UTOPIA Level 2 Interface Specification • ATM Switches • Supports 8 or 16 Bit UTOPIA Bus Operating at 25MHz or 33MHz or 50MHz •

Contextual Info: XRT7300 E3/DS3/STS-1 Line Interface Unit September 1999-2 FEATURES l Single-chip Transmit and Receive Line Interface IC for E3 34.368Mbps , DS3 (44.736Mbps) and SONET STS-1 (51.84Mbps) Applications l l Transmit Interface Characteristics l Accepts Either Single Rail or Dual Rail Data

Contextual Info: áç XRT7300 E3/DS3/STS-1 LINE INTERFACE UNIT SEPTEMBER 2000 REV. 1.0.7 FEATURES • Meets E3/DS3/STS-1 Jitter Tolerance Requirements GENERAL DESCRIPTION The XRT7300 DS3/E3/STS-1 Line Interface Unit is designed to be used in DS3, E3 or SONET STS-1 applications and consists of a line transmitter and receiver integrated on a single chip.

Contextual Info: XRT7300 E3/DS3/STS-1 Line Interface Unit m t FEATURES • Single-chip Transmit and Receive Line Interface 1C for E3 34.368Mbps , DS3 (44.736Mbps) and SONET STS-1 (51,84Mbps) Applications Transmit Interface Characteristics • Accepts Either Single Rail or Dual Rail Data

ATM microcontrollers

Abstract: XR-7234A XR-7234B atm receiver multi-bit error header INCOMING MATERIAL FLOW PROCESS Pin-for-Pin Compatible with the
Contextual Info: Preliminary XR-T7234 «✓ Z * E X A E3 UNI User Network Interface 1C for ATM R December 1997-1 FEATURES APPLICATIONS • Compliant with UTOPIA Level 2 Interface Specification • Supports 8 or 16 Bit UTOPIA Bus Operating at 25MHz or 33MHz or 50MHz • User Programmable Cell Filter

D15C

Abstract: XR-T7245A XR-T7245B atm receiver multi-bit error header
Contextual Info: Preliminary XR-T7245 «✓ Z * E X A DS3 UNI User Network Interface 1C for ATM R December 1997-1 FEATURES APPLICATIONS • C om pliant w ith U T O P IA Level 2 Interface S pecification • Supports 8 or 16 Bit U T O P IA Bus O perating at 25M H z or 33M H z or 50M H z

Contextual Info: I ABOUT EXAR I PRODUCTS I INDEX I SALES INFORMATION I INFORMATION REQUEST I SEARCH I HELP I DS3/E3 Product Selector Guide DS3/E3 Products DS3/E3 Line Interfaces Part No. #of Channels Data Rates Clock Recovery Temp Range Operating Power Supply Max Current Package s

225feet

Contextual Info: XRT7300 E3/DS3/STS-1 LINE INTERFACE UNIT MAY 2011 REV. 1.1.2 GENERAL DESCRIPTION FEATURES • Meets E3/DS3/STS-1 Jitter Tolerance Requirements The XRT7300 DS3/E3/STS-1 Line Interface Unit is designed to be used in DS3, E3 or SONET STS-1 applications and consists of a line transmitter and receiver integrated on a single chip.

Contextual Info: XRT7300 E3/DS3/STS-1 Line Interface Unit January 2000 FEATURES l Single-chip Transmit and Receive Line Interface IC for E3 34.368Mbps , DS3 (44.736Mbps) and SONET STS-1 (51.84Mbps) Applications l l Transmit Interface Characteristics l Accepts Either Single Rail or Dual Rail Data

0X00

Abstract: GR-253-CORE GR-499-CORE XRT7300 XRT7300IV
Contextual Info: áç XRT7300 E3/DS3/STS-1 LINE INTERFACE UNIT FEBRUARY 2002 REV. 1.1.1 FEATURES • Meets E3/DS3/STS-1 Jitter Tolerance Requirements GENERAL DESCRIPTION The XRT7300 DS3/E3/STS-1 Line Interface Unit is designed to be used in DS3, E3 or SONET STS-1 applications and consists of a line transmitter and receiver integrated on a single chip.

Contextual Info: Preliminary y » c w XR-T7234 E3 UNI User Network Interface 1C for ATM j R • %. .the analog plus company June 1997-3 FEATURES APPLICATIONS Compliant with UTOPIA Level 2 Interface Specification ATM Switches Supports 8 or 16 Bit UTOPIA Bus Operating at

Contextual Info: ABOUT EXAR I PRODUCTS I INDEX I SALES INFO I INFORMATION REQUEST I SEARCH I HELP I DS3/E3 Product Tree Click one of the links below to go to that product page DS3/STS-1/E3 Receiver XRT7295 XRT7295E Transmitter XRT7296 XRT7298 Transceiver XRT7300 1ch XRT73L00 (1ch)

0X00

Abstract: GR-253-CORE GR-499-CORE XRT7300 XRT7300IV 24-BNC T3001
Contextual Info: áç XRT7300 E3/DS3/STS-1 LINE INTERFACE UNIT JUNE 2001 REV. 1.1.0 FEATURES • Meets E3/DS3/STS-1 Jitter Tolerance Requirements GENERAL DESCRIPTION The XRT7300 DS3/E3/STS-1 Line Interface Unit is designed to be used in DS3, E3 or SONET STS-1 applications and consists of a line transmitter and receiver integrated on a single chip.

Contextual Info: XRT7300 E3/DS3/STS-1 Line Interface Unit September 1999-2 FEATURES l Single-chip Transmit and Receive Line Interface IC for E3 34.368Mbps , DS3 (44.736Mbps) and SONET STS-1 (51.84Mbps) Applications l l Transmit Interface Characteristics l Accepts Either Single Rail or Dual Rail Data

Contextual Info: áç XRT7300 E3/DS3/STS-1 LINE INTERFACE UNIT JUNE 2000 REV. 1.0.5 GENERAL DESCRIPTION The XRT7300 DS3/E3/STS-1 Line Interface Unit is designed to be used in DS3, E3 or SONET STS-1 applications and consists of a line transmitter and receiver integrated on a single chip.

Contextual Info: XRT7300 E3/DS3/STS-1 Line Interface Unit September 1999-2 FEATURES l Single-chip Transmit and Receive Line Interface IC for E3 34.368Mbps , DS3 (44.736Mbps) and SONET STS-1 (51.84Mbps) Applications l l Transmit Interface Characteristics l Accepts Either Single Rail or Dual Rail Data