A 9050 14 Search Results

plx 9052

Abstract: A 9050 14 pci 9052 9050-1
Contextual Info: PCI 9050 Errata Rev. 1.3 August 2001 Errata Documentation A. Affected Silicon Revision This document details errata in the following silicon: Product PCI 9050 B. Part Number PCI 9050-1 Description 160-pin PQFP Package Status Production Released Silicon Documentation Revision

Contextual Info: PCI 9050-1 Datasheet Version 1.01 April, 17, 1997 Website/ftp Site: http://www.plxtech.com Email: apps@plxtech.com Phone:408-774-9060 F A X :408-778-2169 PCI 9050-1 TABLE OF CONTENTS TABLE OF CONTENTS 1. GENERAL DESCRIPTION. 1

xr-9050

Contextual Info: V ? E X A XR-9050 R Data Synchronization 11,7 RLL ENDEC Preliminary Information GENERAL DESCRIPTION PIN ASSIGNMENT a The XR-9050 is a high-speed, single +5V supply, low pow er fu lly in te g ra te d 1,7 ENDEC and Data Synchronizer. It is a com plete system for data

Contextual Info: X^EXqR XR-9050 Data Synchronization 11,7 RLL ENDEC Preliminary Information PIN ASSIGNMENT GENERAL DESCRIPTION The XR-9050 is a high-speed, single +5V supply, low pow er fully in teg rated 1,7 E N D E C and D ata Synchronizer. It is a complete system for data

Contextual Info: Photocells A 9050, A 9060 Epoxy encapsulated series Light Switch Appliactions Indoor and Outdoor This Photocell series includes two different spectral sensitivity ranges. The A90. range is the smallest size of photocell in epoxy encapsulation. Customized

switch photocell

Abstract: A9060-12 A906011 A906012 A906009 A905014 A906013 A9060-09 photocell sensor A 9050 14
Contextual Info: | Sensors | D A T A S H E E T Sensor systems Lighting p Ambient Light Sensing Applications Photocells A 9050, A 9060 Epoxy encapsulated series Light Switch Appliactions Indoor and Outdoor This Photocell series includes two different spectral sensitivity ranges. The

Contextual Info: PCI 9050 TE August 31, 1996 VERSION 1.0 PCI Bus Target Interface Chip for Low Cost Adapters Featu res_ General Description_ • PCI Specification 2.1 Com pliant Target Interface Chip supporting low cost slave adapters. A llow s simple

FDMF6704

Abstract: FDMF6704A FDMF6704V power loss Effio
Contextual Info: www.fairchildsemi.com AN-9050 FDMF6704 Power Loss Calculation YoungSub Jeong Introduction The FDMF6704 DrMOS MCM Multi Chip Module product has HS and LS FETs and a gate driver all contained within a single module. The design has been optimized for Synchronous Buck applications. The switching and

ISA slot

Abstract: plx 9050 c 9050 plx9050 9050
Contextual Info: PCI 9050RDK Reference Design Kit Features • PCI Version 2.1 compliant board based on the powerful PLX 9050 Bus Target Interface Chip ■ PCI 9050RDK available for both Generic and ISA Bus Adapters ■ PLXMon 95 provides a comprehensive tool for PCI bus monitoring and debug.

Z89300

Abstract: Z89302
Contextual Info: P R E L I M I N A R Y Z8930200TSC CPS DC-9050-00 PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION Z8930200TSC EMULATION MODULE PROTOPACK DESCRIPTION KIT CONTENTS The Z8930200TSC Emulation Module allows the user to plug programmed EPROMs into the board to verify operation of code before submitting for mask ROM.

IRC FA series resistor

Abstract: EARTH LEAKAGE RELAY
Contextual Info: G l N I KAI IN S IK l M l ISTI AY-5-9050 Five Channel Relay Driver/High Voltage Interface FEATURES • Reference voltages generated and regulated o n -ch ip from a single pow er supply High noise im m unity High re lia b ility and low cost using P-channel M TNS process

20100N

Abstract: panasonic diode 2kw mosfet BAT54 FDS6690A FZT649 ISL6449CB ISL6449CB-T TB363 TB379
Contextual Info: ISL6449 TM Data Sheet November 2001 Dual Regulator - Standard Buck PWM and Linear Power Controller for Gateway Applications File Number 9050 Features The ISL6449 provides the power control and protection for two output voltages, such as those required in highperformance gateway processor applications. The dualoutput controller drives an N-Channel MOSFET in a

Contextual Info: G f'M U A I INSI RI M i IVI AY-5-9050 Five Channel Relay D river/High Voltage Interface FEATURES • Reference voltages generated and regulated o n -ch ip from a single pow er supply H igh noise im m unity H igh re lia b ility and low cost using P-channel MTNS process

ESS 9018

Abstract: PC Jack
Contextual Info: P.C. J A C K S-C L O SE D EN TRY-BO LDER MOUNT 09-9050-1- XX P.C. JACK FOR .016 THRU .019 FINISH OR .020 ONLY, PINS* B A S IC P A R T NO. 09-9026-2-XX P.C. JACK FOR .016 THRU .019 BASIC P A R T NO. FINISH OR .02 0 ONLY, PINS* d m in h o l e r 5- °°sDEPTH

S30E4A

Abstract: S30E14A S30E12A S30E16A S30E12B ST330C16C S23A14A S30E14B S30E10A ST330C14C
Contextual Info: 4fl5S45H G01G70b 1 • ZtaE D INTERNATIONAL R E C T IF IE R International Ixo rI Rectifier Phase Control Thyristors 470 TO 1420 AMPS RMS Part v number v RRM *T RMS ' t (AV) tc GT TM ’g t (3) 50Hz 60Hz (2) DRM (V) (TSM (A) (A) (°C) (A) (A) (2) (mA) (V)

S30E14A

Abstract: S30E4A S30E14B S30E16A S30E20A S30E12A S23A14A S30E18A S23A4B S30E8B
Contextual Info: Thyristors International i« » ! Rectifier Phase Control Type 470-1420 Amps RMS Part Number ST230C02C ST230C04C ST230C06C ST230C08C ST230C10C ST230C12C ST230C14C ST230C16C S23A2A S23A2B S23A4A S23A4B S23A6A S23A6B S23A8A S23A8B S23A10A S23A10B S23A12A S23A12B

PCI9050

Abstract: 38e9 c 9050 10B5 93CS56 NM93CS46 PCI-9050-1
Contextual Info: PCI 9050 August 31, 1996 PCI Bus Target Interface Chip for VERSION 1.0 Low Cost Adapters Features_ • • • • • • • • PCI Specification 2.1 Compliant Target Interface Chip

AD17

Abstract: 9050R la18
Contextual Info: PCI 9050 Bus Target Interface Chip Features • PCI Specification 2.1 Compliant Target Interface Chip supporting low cost slave adapters ■ Up to five local bus address spaces and four chip selects ■ Bi-directional FIFO for zero wait-state burst operation

AD27

Abstract: AD29 AD30 PCI Backplane Block Diagram
Contextual Info: PCI 9050 Bus Target Interface Chip Features • PCI Specification 2.1 Compliant Target Interface Chip supporting low cost slave adapters ■ Up to five local bus address spaces and four chip selects ■ Bi-directional FIFO for zero wait-state burst operation

Contextual Info: ANALOG DEVICES FEATURES Low Power: 315 mW On-Chip T/H , Reference Single +5 V Power Supply Operation Selectable 5 V or 3 V Logic I/O SNR: 53 dB Minimum at 10 MHz 10-Bit, 40 MSPS ADC AD9050 FUNCTIONAL BLOCK DIAGRAM tav AD9050 REFERENCE CKTS A IN B O - APPLICATIONS

Contextual Info: 10-Bit, 40 MSPS/60 MSPS A/D Converter AD9050 a FU NCTIONAL B LOCK D IAGRAM FEATURES Low Pow er: 315 mW @ 40 M SPS, 345 mW @ 60 M SPS On-Chip T/ H, Reference Single +5 V Pow er Supply Operation Selectable 5 V or 3 V Logic I/ O SNR: 53 dB M inimum at 10 M Hz w / 40 M SPS

0x9050 0x10b5

Abstract: 8BA22 LA2780 PLXMON95 10B5 BD28 MACH210 NM93CS46 9050RDK PLX9050
Contextual Info: PCI 9050RDK Development Kit Manual Version 1.2 January 28, 1998 Product Sales: 1- 800 -759-3735 Fax: 1- 408-774-2169 Email: info@plxtech.com Web and FTP Site: //www.plxtech.com T E C H N O L O G Y Table of Contents Preface . vii

Contextual Info: ANALOG DEVICES FEATURES Low Power: 315 mW On-Chip T/H, Reference Single +5 V Power Supply Operation Selectable 5 V or 3 V Logic I/O SNR: 53 dB Minimum at 10 MHz 10-Bit, 40 MSPSADC AD9050 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Medical Imaging Instrumentation

P-CDL

Abstract: D0014S3 10B5 38E9 93CS56 NM93CS46 PCI9050
Contextual Info: Æ Q C * . P T e c T H T S -rS -S T X August 31, 1996 VERSIO N 1.0 C 9 I 5 PCI Bus Target Interface Chip for Low Cost Adapters Featu res_ General Description_ • PCI Specification 2.1 Com pliant Target Interface Chip