A0-A12, D0 SRAM Search Results

Contextual Info: CY7C199-45PC 1/2 IL00D C-MOS 256 K (32,768 x 8)-BIT SRAM —TOP VIEW— 21 A5 1 VDD 28 A6 2 27 A7 3 26 A4 A8 4 25 A3 A9 5 24 A2 23 24 WE 25 26 1 2 3 4 5 6 A10 6 23 A1 7 8 A11 7 22 OE 9 10 A12 8 21 A0 A13 9 20 CE A0 D0 A1 D1 A2 D2 A3 D3 A4 D4 A5 D5 A6 D6 A7

4000B

Abstract: ANH006A
Contextual Info: PUMA68 COTS Pinout SRAM Summary One of the key features of the PUMA (Pinned Uncommitted Memory Array) product range is its well defined upgrade path Pin Definition The PUMA68 product range provides a lower cost, footprint compatible, alternative to the well

D28A0

Abstract: pinout 4001 ANH001A
Contextual Info: PUMA2 Pinout SRAM and EEPROM Summary One of the key features of the PUMA Pinned Uncommited Memory Array product range is its well defined upgrade path. Pin Definition Assuming the relevant address lines are routed on the system board, upgrade may be achieved by simply removing a device and replacing it with the next generation part.

d28 diode

Abstract: 4000B ANH003A D-13
Contextual Info: PUMA 67 / 77 Pinout SRAM Summary One of the key features of the PUMA Pinned Uncommitted Memory Array product range is its well defined upgrade path. Pin Definition Assuming the relevant address lines are routed on the system board, upgrade may be achieved by simply removing a device and replacing it with the next generation part.

STK12C68-S45

Contextual Info: STK12C68-S45 1/2 IL08D C-MOS 64 K (8,192 x 8)-BIT NONVOLATILE SRAM —TOP VIEW— E CAP IN 1 VDD 10 28 9 8 A12 IN 2 27 WE IN 7 6 A7 IN 3 26 HSB IN A6 IN 4 25 A8 IN A5 IN 5 24 A9 IN 5 4 3 25 24 21 A4 IN 6 23 A11 IN 23 2 OE IN A3 IN 7 22 A2 IN 8 21 A10 IN 26

ANH009

Abstract: 84SV PUMA84 CS-7
Contextual Info: PUMA84 Pinout SRAM and FLASH Summary One of the key features of the PUMA Pinned Uncommitted Memory Array commercial product range is its well defined upgrade path. Pin Definition The following table defines the pins Pin 84S/SV 32000 84SV 64000 84FV 128006

Contextual Info: STK10C68-5S35 1/2 IL22D C-MOS 8 K x 8-BIT NONVOLATILE SRAM —TOP VIEW— 10 NE IN 1 VDD 28 9 8 A12 IN 2 A7 IN 3 27 WE IN 7 6 NC 26 5 4 A6 IN 4 25 A8 IN 3 25 A5 IN 5 24 A9 IN 24 21 A4 IN 6 23 A11 IN 23 2 A3 IN 7 22 OE IN A2 IN 8 21 A10 IN A1 IN 9 20 CE IN

block diagram of of TMS320C4X

Abstract: 8L32512
Contextual Info: EDI8L32512C 512Kx32 SRAM Module 512Kx32 CMOS High Speed Static RAM Features DSP Memory Solution • Motorola DSP96002 • Analog SHARC DSP • Texas Instruments TMS320C3x, TMS320C4x Random Access Memory Array • Fast Access Times: 12*, 15, 17, and 20ns The EDI8L32512C is a high speed, 5V, 16 megabit SRAM.

ANH008A

Contextual Info: PUMA68 Pinout SRAM and EEPROM Summary One of the key features of the PUMA Pinned Uncommited Memory Array commercial product range is its well defined upgrade path. Pin Definition The following table defines the pins : Pin 68S/SV 4000X 68S/SV 16000XB 68S/SV

U29B

Abstract: C111 C115 C218 C303 C304 C332 C334 sram128kx8
Contextual Info: D C B A 4 S_A[18:2] RAM_CNTL 4 S_OE# S_WE# SRAM3_CE# S_A[18] S_A[17] S_A[16] S_A[15] S_A[14] S_A[13] S_A[12] S_A[11] S_A[10] S_A[9] S_A[8] S_A[7] S_A[6] S_A[5] S_A[4] S_A[3] S_A[2] 28 12 5 13 14 15 16 17 18 19 20 21 29 30 31 32 1 2 3 4 SRAM2_CE# 28 12 5 13

d2388

Abstract: Intel-PENTIUM-PROCESSOR vlsi technology cwe4 block diagram of pentium D Burndy INTEGRATED DEVICE TECHNOLOGY 71V432
Contextual Info:  Integrated Device Technology, Inc. 256KB AND 512KB SECONDARY CACHE MODULES FOR THE INTEL PENTIUM CPU AND VLSI WILDCAT CORE LOGIC PRELIMINARY IDT7MPV6239 IDT7MPV6240 IDT7MPV6241 IDT7MPV6244 high-speed 16-bit IDT FCT logic, and the IDT7MPV6241/44 use IDT's 71V432 32Kx32 pipelined burst SRAMs in plastic

Contextual Info: MB84256-10LP IL08 C-MOS 256 K 32,768WORD x 8 -BIT SRAM —TOP VIEW— 10 A14 IN 1 VDD 28 A12 IN 2 27 9 WE IN 8 7 A7 IN 3 26 A13 IN 6 A6 IN 4 25 A8 IN 5 A5 IN 5 24 A9 IN A4 IN 6 23 A11 IN A3 IN 7 22 OE IN 4 3 25 24 21 A2 IN 8 21 A10 IN A1 IN 9 20 CS IN 23

Contextual Info: 512K x 32 SRAM MODULE PUMA 2/77S16000/A - 020/025/35 Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear NE29 8SE, England Tel. +44 0191 2930500 Fax. +44 (0191) 2590997 Issue 4.4 : April 2001 Description 16,777,216 bit CMOS High Speed Static RAM Available in PGA (PUMA 2 ) and Gullwing (PUMA 77) Features

Contextual Info: 512K x 32 SRAM MODULE PUMA 2/77S16000/A - 020/025/35 Issue 4.4 : April 2001 Description 16,777,216 bit CMOS High Speed Static RAM Available in PGA PUMA 2 and Gullwing (PUMA 77) Features footprints, the PUMA *S16000 is a 16 MBit SRAM • 16MBit Fast SRAM Module.

2S4000

Contextual Info: 128K x 32 SRAM Module PUMA 2/67S4000/A-020/025/35 Issue 4.4 : April 2001 Description Features Available in PGA PUMA 2 and JLCC (PUMA 67) footprints the PUMA *S4000 is a 4 Mbit SRAM module, user configurable as 128K x 32, 256K x 16 or 512K x 8. The device is available with fast access

Contextual Info: 128K x 32 SRAM Module PUMA 2/67S4000/A-020/025/35 Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear NE29 8SE, England Tel. +44 0191 2930500 Fax. +44 (0191) 2590997 Description Features Available in PGA (PUMA 2) and JLCC (PUMA 67) footprints the PUMA *S4000 is a 4 Mbit SRAM

77S16000

Contextual Info: 512K x 32 SRAM MODULE PUMA 2/77S16000/A/B - 020/025/35 Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear NE29 8SE, England Tel. +44 0191 2930500 Fax. +44 (0191) 2590997 Issue 4.5 : September 2002 Description 16,777,216 bit CMOS High Speed Static RAM Available in PGA (PUMA 2 ) and Gullwing (PUMA 77) Features

d666

Abstract: CRX14 STM1404 st nand flash application note firmware cash register JTCK STEVAL-IPC001V1 STR710FZ2 A6 P113
Contextual Info: STEVAL-IPC001V1 Electronic fiscal cash register Data Brief Features • 4-Mbyte Flash, 32-Mbyte NAND and 1-Mbyte SRAM on board ■ Two smartcard readers ■ STM1404 secure chip, FIPS 140-2 compliant ■ Ethernet 10Base-T, 3 UARTs, 1 RS-485, 1 PS/ 2, 1 USB full speed, 4 x I2C, 1 x SPI, 2 LCDs

Contextual Info: 512K x 32 SRAM MODULE PUMA 2/77SV16000/A - 020/025/35 Issue 1.1 : April 2001 Description 16,777,216 bit CMOS High Speed Static RAM Available in PGA PUMA 2 and Gullwing (PUMA 77) Features footprints, the PUMA *SV16000 is a 3.3V 16 MBit • 16MBit Fast SRAM Module.

Contextual Info: 128K x 32 FLASH Module PUMA 67F4006/A - 70/90/12 11403 West Bernado Court, Suite 100, San Diego, CA 92127. Tel No: 001 858 674 2233, Fax No: (001) 858 674 2230 Issue 1.0 : February 2000 Description Features • 4 Megabit FLASH module. The PUMA 67F4006 is a 4 Mbit SRAM module,

Contextual Info: 128K x 32 SRAM Module TIGA2S4000 -20/25/35 TIGA6S4000/A/B-20/25/35 TIGA7S4000/A/B-20/25/35 Force Technologies Ltd. www.forcetechnologies.co.uk Tel. +44 0 1264 731200 Fax. +44 (0)1264 731444 Issue 1 2005 Description Features Available in PGA (TIGA 2), JLCC (TIGA 6) and

Contextual Info: 128K x 32 SRAM Module Elm Road, West Chirton, North Shields, Tyne & Wear NE29 8SE, England Tel. +44 0191 2930500 Fax. +44 (0191) 2590997 Description PUMA2S4000 -20/25/35 PUMA 67S4000/A/B-20/25/35 PUMA 77S4000/A/B-20/25/35 Issue 4.5 : August 2002 Features

2S4000

Abstract: PUMA 77S4000 67S4000 S4000 2S400 PUMA77S4000
Contextual Info: 128K x 32 SRAM Module Elm Road, West Chirton, North Shields, Tyne & Wear NE29 8SE, England Tel. +44 0191 2930500 Fax. +44 (0191) 2590997 Description PUMA2S4000 -20/25/35 PUMA 67S4000/A/B-20/25/35 PUMA 77S4000/A/B-20/25/35 Issue 4.5 : August 2002 Features

74HC08

Abstract: 74HC04 application note 74HC04 NOT GATE datasheet 74HC04 74HC04 Toshiba MC68EZ328 a5d5 yc 428 TC554161FTL TC554161FTL-85
Contextual Info: Order this document by TBD Date: 11/12/98 DragonBall Operation Preliminary Application Note 16bit SRAM Interface INTRODUCTION This note describes the method of interfacing a 16bit SRAM to DragonBall-EZ MC68EZ328 . The interface is simply constructed by discrete logic gates.